The last old timer engineer retired not to long ago at our location and that just leaves me and two others now. Looking at the business structure where I am, I maybe considering splitting paths and starting something on my own. The old timer that retired was open minded and was pretty sharp himself. He since moved, left the state to a much cheaper place to live in. :)
------------------ Getting back at the subject at hand -----------
I was looking at some DMOS depletion fets not to long ago, since those seem to be a better choice. The main problem with these are the same as working with JFETS, current limited states and R(on) states. I guess if you can find one that will deliver the max (Ids) before it folds back and does not incur to much R(on) and stay away from LDO, then you're all set. Other issues is the thermo's in these types and bias stability.
One of our projects has a row of NMOS enhanced power fets operating in a linear circuit, mounted on a deep heat sink that sits in a cooled glycol system, just to keep the circuit stable so the biasing does not wander to much.
Maybe I'll have purchasing department get me a few tubes of various depletion types and conduct some real time experiments.
Jamie