SillyAmp

One could ac couple, unless it's a DC amplifier, then back to two parts is better. The pnp is an mpsa92.

Winfield Hill a écrit :

That one has a highly optimized 2nd order distortion. Should sound good and satisfy the most exigent tube aficionados :-)

How about a feedback resistor from "OUT" to PNP(e) ??

But there's probably not enough loop gain to reduce the distortion by much.

...Jim Thompson

Jim Thompson a écrit :

Before doing that, you'll need to properly bias the input stage. Exercise left to the student :-)

Are there any "students" here? They certainly don't step forward and attempt to learn :-(

...Jim Thompson

Mini-nits: both my optocouplers were the same, npn's, and my input-side supplies were +-2, to keep idle current down:

Is not! You're just jealous that you don't have 400 volt optocouplers in any of your ic libraries.

John

Actually, it's not so bad with a significant Rs. That's because the power high-voltage MOSFET will be operating in its sub-threshold region, where its gm is nearly as high as a BJT at the same current. With the high supply voltage and a modest ratio RL/Rs =3D 50, for 500V out with 10V in, Rs > 1/gm will keep the distortion under control.

Actually, as mentioned above, with Rs =3D 0, the loop gain could be sizeable, and rightly, done it could work reasonable well. The pullup capabillty is rather wimpy and there are several DC offset sources.

A real circuit would be more complicated, like some I've posted before, including an opamp, a totem-pole pullup transistor, current limiting, and compensation.

I was just referring to the absence of bias for the PNP, assuming the input signal was symmetric :-)

I'd probably reduce the 2.2M to 22k or such, which is about 200uA and

Yep, but be careful, that 200uA would have to come from the PNP summing junction, making a high output offset to correct. Maybe 2.2M is too high, but consider, Crss is only 3pF for an FQP1n60 above Vds =3D 25 volts, and with Vgs about 3 volts at Id =3D 2mA, we get a rising slew rate of S =3D I/C =3D Vgs/RC =3D 0.5V/us. 220k would give us 5V/us. If this stage is placed inside an opamp feedback loop, then we can begin to get aggressive about the currents. Unless a pullup transistor is added, external capacitive loads will seriously slow down this wannabe beast anyway.

I'd feel better if there was a gate zener, and maybe a resistor in series with the PNP collector; I hate all-silicon paths from -260 to ground. Then go ahead and add a source resistor, to get some current limiting and improve linearity.

If you want silly, how about an optocoupler/mosfet cascode? Or better, ie sillier, an opto+depletion fet cascode!

Actually, that's getting interesting.

John

John Larkin a écrit :

I thought about that last one as a replacement to the HV optos when you first 'published' your idea here a couple of years ago. But now that's 4 active parts. Well six, including the leds.

The zener is mandatory. Diode protection for the PNP, yep. Safety current limiting is wise, although after making hundreds of such amps with mpsa92 trannies, I had only one failure and it blew the mpsa92 wide open. Lots of energy stored in the supply caps after all.

v+ | | r | +-----------out | | d in---------+ g ---+ | s | | | | a c | k ---> b | | opto e | | | | gnd +-----+----- v-

Apex, cry your heart out.

John

v+ | | r | +-----------out | | Supertex d depletion-mode in--/\/\---, g ---, | s | | | | a c | k ---> b | | opto e | | | | gnd +-----+----- v-

Awesome. Don't forget a resistor for the opto.

Another silly KYAG circuit ;-)

...Jim Thompson

?? Really? KYAG? How so? ?? That looks like a relatively-well behaved circuit, with excessive gain. But it does cry out for a feedback loop.

Concern for opto NPN punch thru during power-up... I could go for a zener or some-such in there.

I've been musing really retro... maybe a mixed toob/silicon amplifier stage ;-)

...Jim Thompson

Silly man. No HV power supply I'm aware of has a fast enough risetime at power-up to come close to creating such an issue. Maybe if one was to use a HV switch in the power supply line, but then the blame would lie in using the switch (been there, done that, oops), not with the circuit. There is a danger if (when) the output is instantaneously shorted, ameliorated with a small output R.

____ V+ hv --o o-----, +200 | 150k, 2W | +/-170V +---- 2.2k -------out | | Supertex DN2540 d depletion-mode g ----, s | in--/\/\---, | 10V | | +--| b | k | e | | | | ____ V- gnd ---+-------+---o o---- -180

A higher-voltage version (+/-300V output) can be made with a Supertex dn2470. That's a 700V depletion-mode MOSFET, the record holder for such parts. Mouser stocks 'em.

This circuit would benefit from feedback. A Darlington NPN would minimize the feedback-node bias current, and an offset resistor could provide for bipolar inputs and correct for the LED and BJT drops at the summing junction. A resistor, say Vgs/I = 470 ohms, in the MOSFET's path would limit the pulldown current to a few mA, to avoid overheating the FET.

V+ hv --/\/\---/\/\---, John's HV amp idea +360 150k, 2W (2) | | Rf/Rin = 60 +/-300V ,- Rf--+ to 1mA Roffset | +---- 3.3k ----------- OUT +5 ----/\/\-----+ | Rin | | Supertex DN2470 IN ----/\/\------+ d depletion-mode -5 to +5 | g ----, | s | | | 10V | +5 --/\/-- c | +--|

On Mar 23, 4:37 am, "Winfield Hill" wrote: [....]

I'm going to suggest a modification or two:

Modified version

Adding the diode (or diodes) marked "NEW" partially compensates for the EB drop of the bipolar transistor.

If instead of a diode, we make that the E-B drop of a PNP emitter follower, we can use a non darlington for the NPN feeding the LED.

If we place a resistor in parallel with the LED we can run the NPN feeding it at a more well known current. This would make matching it with the PNP better.

The capacitance of the 10V zener slows things down.

Many K +V---/\/\----- ! 10V ------->!-----+----!