1. Home
  2. Electronics Design
  3. Advice on a CMOS d flip flop frequency divider..

Advice on a CMOS d flip flop frequency divider..

Hi all.. Its been quite awhile since my college courses on logic design, so I just wanted to run something by you..

I need a simple /2 frequency divider. Input/output voltages require CMOS.. Input frequency on D would be a varying 0-175hz of a 0-14vdc square wave at 50% duty cycle.. Output voltages and duty cycle would be as input, just 1/2 the freq.

Im looking at an MC14013B from ON Semi (datasheet:

formatting link
) ..

I'd planned on just tying my Input to my clock in order to keep things as simple as possible.. but was wondering if this would cause any issues?

Its going to be in a car, so Id figured on zeners on the VCC, clock and Input lines to keep things safe in case of regulator failure..

Does anyone see any glaring errors here?

thanks for any assistance you can offer,

nopk.

Reply to
nopk73
Loading thread data ...

(datasheet:

formatting link
..

The normal way to do a divide-by-two with a D f/f is to use the input to clock the f/f, and tie the D input to the /Q output. If you tie the input to D, what will you use to clock it? If you tie D and the clock together, you're asking for a race condition, and it wouldn't do what you want anyway.

You can get some big spikes on a car's nominally 12V power...beware. CMOS will run on a very tiny amount of power; if you can stand a bit lower output voltage, consider putting in maybe a 10V zener and a resistor from the "12V" to that zener; run the circuit from the 10V.

Cheers, Tom

Reply to
Tom Bruhns

Thanks for your reply Tom..

It took me a couple minutes to re-wrap my head around your description.. but am now clued in to what you're saying..

Unfortunately, Im also now clued in to exactly how much Ive forgotten from my old electronics classes heh.. after reading your desc. I grabbed some paper and worked through what MY original idea wouldve done.. realizing having done that, that (depending on timing of things) I'd be clocking in a random 0 or 1 depending on where the Input was as Clock saw the rising edge (as I had indeed planned on tying Clock and D together.. doh)..

I do have one question though.. as the CMOS IC will take up to 18vdc inputs, whats the reasoning behind using a 10vdc zener instead of say a 12 or 13vdc item and not losing that additional voltage?

thanks again for the help,

nopk

Reply to
nopk73

(snip sorting out D-type F/F divide-by-two)

What benefit do you think running at a higher voltage gives?

You'll get more speed, and more noise immunity - but neither is as important IMOE as getting safe operation with the prospect of assured input swing. What you may not have picked up from Tom's response is the need to clamp the input swing to avoid excursion above the Vcc rail. A simple series-R and a diode to that rail will suffice.

(I normally use a 9V reg on automotive logic, but if you want reliable operation under all conditions you'll probably need to locate a low dropout type).

Reply to
budgie

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.