is it possible to run ADC's in parallel to get increased sample rate?
I.e.
Signal ----+--> ADC1 ------------>
| +-- Delay --> ADC2 --->
so each ADC runs, lets say, at M mhz and Delay is a delay of 1/(2*M) seconds. So in a sense ADC2 samples "inbetween" what ADC1 samples. This would effectively increase the sampling rate by 2? I'm sure that the delay would have to be designed almost perfectly so that no distortion would arise because the samples would be expected to be equally spaced?
Yes, but instead of delaying the analog signal you usually use out of phase conversion clocks so that they take turns producing digital output, then multiplex that output. (Or for very high speed systems, you don't multiplex it until you have to - some of the high speed ADC's actually demultiplex their output to two paths to keep the signal rates on the PCB interconnect more reasonable)
Some of the issues would be keeping a clean phase relationship between the two sample clocks, jitter of those clocks, and jitter of the coverter's response to the clocks. Also the bandwidth of your input circuitry and the converter input (sample and hold, whatever) has to be high enough.
The makers of high speed ADC's (national, analog devices, etc) tend to have application notes on how to do this.
You don't need a delay, you need both ADCs to have sample times equal to the new, higher sampling rate, and then you need to clock them appropriately. If your ADCs are both bandwidth limited to the original rate, there's no point in using two of them.
Whenever I had to design something like this I found that they didn't have much about that topic. The trick is to auto-align three things: Amplitude (easy), offset (pretty easy), clock timing (not easy at all).
I am in the process of writing a publication about that. As usual, this has to be done outside work so it'll take a while. Will either be through IEEE if they accept or if they don't it'll be on my web site.
All the medium-to-high-speed digital scopes do this (except the non-realtime, equivalent-time samplers of course.) I think one of the Agilent 12-ish GHz scopes, the $100K monster, has something like 256 ADCs in the front end. And aligning them must be a real bear.
That's probably why it costs that much. Once you have a working scheme it's just duplicated over and over. One reason why I am a bit stuck on this paper is that the FETs of yesteryear have become rare and expensive. IMHO publishing something only makes sense if people can actually build it with contemporary and reasonably priced parts.
Luckily I found that they still make dual-gate MOSFETs for TV tuners. Unfortunaly they aren't strictly enhancement types, more of a mixed breed between enhancement and depletion mode. Anything else is big these days. Low Rdson is the name of the game but that comes with capacitances that are prohibitive here. The downside of these TV transistors is that they are true hot-rods. A few picohenries at the wrong spot and they sing.
Wanted to continue today but can't concentrate. Just had the 2nd part of a molar root canal done and after the novacain wore off the pain is intense. With the weekend coming up I just hope it won't go off on me. Then again this is nothing compared to what Jim's son is now going through.
I don't know what you're doing, but might a dual-gate mesfet help? NE25339 or some such. They're depletion mode, but the capacitances are tiny.
And I always keep a hoard of opiates (Vicodin, Tylenol C), spares from previous horrors, around for emergencies like tooth troubles and, um, unmentionable infections.
There's a report out today that as little as a double dose of Tylenol can destroy your liver.
Personally, I'm allergic to the stuff... one tablet and I can't focus my eyes and I feel dizzy.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Basically a controlled resistor to create a 'gliding delay adjuster'. What many people don't realize is that it ain't enough to provide equi-distant clocks. In high precision apps one has to mind the aperture latency of each ADC and this can be a few hundred psec. Most of the time it isn't even specified, they only state a typical value so you have to provide lots of adjustment range. This uncertainty really hits when you find ADCs from different production lots on one board.
Thanks for the hint, I'll check out the NE25339. There is one downside though. Neither Arrow nor Digikey, Mouser or Newark carry it so people who want to kick the tires may not be able to buy it. Depletion mode needs a negative rail which lots of systems don't have anymore these days. Whenever I suggest a lil' CMOS logic oscillator to create a negative supply I can see people developing goose pimples.
The BF998 is nice, around 10c in qties and you can even buy just a few for 50c a pop. It's about a pF for Cds, the only capacitance that really matters in this application. If they made these without protection diodes I'd jump up and down. But that isn't going to happen since they are for tuners.
PIN diodes would be my favorites but in order to move a logic level signal around you need huge carrier lifetimes. Used to be easy to find but not anymore, at least not in the one-dime class.
We had a stash of Motrin. Now it's better, as long as I don't touch the tooth. Maybe a nice Anchor Steam will help, since I am not going to be able to eat a real dinner I'll have an excuse to pop one of these. Or maybe two.
Mouser and Digikey both used to stock it, but it's gone away. Digikey has the NE25139, just a smaller-geometry version.
Are you trying to fine-tune ADC clock edges? You could maybe just shift their DC levels. And LVDS receivers make very nice, fast comparators that can make good time-edge movers.
I think if you do the math on the ADC edge timing, the requirements can get absurd, down in the femtoseconds.
Smaller geometry is sometimes better in these cases. For a tuner transistor it's expensive though which can be a sign that it may be on the way out. At first glance it looks better than the BF99x series if a negative supply is available.
Yes, that's what I am doing. DC shift with logic wasn't so hot when I tried that but LVDS receivers weren't available at that time, or at least not affordable. I'll check that out. The trade-off is that ADCs need low phase noise clocks and when you make the slopes shallower to yield enough adjustment range this noise can be a problem.
The nice thing versus a digital delay line is that an analog approach allows an almost infinitely fine granularity. It can be controlled by a slow 16bit or higher DAC or, gasp, a PWM. Digital delay lines are IMHO quite expensive boutique parts and can be noisy.
That's that variant of the analog storage concept with individual FIR processing to achieve channel equalization -all in some massive mixed mode ASIC or ASICs.
Consider: You get caught in a time warp and get sent back in time to where you can only get 1MHz ADC's, but you need to digitize a certain analog signal at a 10MHz rate in order to get back.
Whatever can you do???
First, set yourself up 10 clocks with the distance between successive leading edges of each clock equal to slightly greater than the conversion time of the ADC, and with the leading edge of each successive clock coincident with the trailing edge of the previous clock, like this:
Then use the leading edge of each clock to latch the result of the previous conversion into a register which corresponds to that channel and to sample the analog signal. Use the trailing edge of the clock to start a new conversion.
The result of this is that you'll have ten conversions occurring in the time it would normally take to get one conversion, so your return to the future can occur.
Actually, just to make sure, you should use 11 ADC's...
I did, on occasion. But it's not the only reason. Sometimes you want to use a FET in a series path and then it needs to stomach +/- whatever the logic level is between gate and the channel.
You wouldn't believe how tough it can be if you want to hang an oscillator onto someone else's design. They perceive that as a switcher (which it kind of is) and have been burned by cheap ones a lot. The answers range from "you've got to be kidding" to "only over my dead body".
Tapping into the analog folks' negative rail, if there is one, is comparably easy. That is because they perceive me as 'one of them'. At least as long as I don't do anything crazy on there, like a switcher :-)
And this seems equivalent to delaying the signal itself? i.e, delaying the signal or delaying the clock is just a relative issue. So is there a technical reason why it is easier to use the clock method than delaying the signal? (i.e., maybe the circuitry to generate the clocks is easier or more stable or whatever)
its all Einsteins fault, what with there being no absolute reference and all :)
the clock approach is (fairly) simple, although as Joerg et al have pointed out, the devil is in the detail if you want high bandwidth and resolution....
delaying the signal would be a far more complex approach, unless the signal was fairly trivial.
Delaying a signal requires precise storage of analog data. Sure, it could be done with CCD or in fast data acquisitions via LC delay lines. However, obtaining any kind of precision will cost an arm and a leg. Think in the three-digit Dollar range.
Clock generation is easy. In John's example you take a 10MHz master clock and a 10-stages deep counter. Regular run-of-the-mills logic chips or a small FPGA. Or use a 20MHz clock if you want to easily make the individual duty cycles 50%. Heck, you could even pour all this into one tiny FPGA plus one external crystal and a couple of caps. Think in the low one-digit Dollar range.
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