ADC "stacking"

Hello John,

Usually you only have to scoot a slope by a few hundred psec. It's not just ADCs. This also needs to be done for pulse transmitters and other things. Cost has to be reasonable, a buck per location would be acceptable, including the discretes but sans DAC. The main concern is long term availability and IMHO the situation does not look good for FET arrays. There must be a reason why their prices crept up and now Arrow and others carry no stock. The big three prototype caterers don't even offer them anymore at all.

No, this is just for a publication. But I don't want to present some elegant academic solution where you can't get the parts.

Jim, or companies like Tektronix that have their own foundries would just roll their own. Us discrete designers have to be able to find it on the shelf. Even weak n-channels like the BSS83 (not the p-channel which unfortunately has the same number) are also becoming rare.

Regards, Joerg

I was thinking about the opposite problem, muxing dac's. Suppose you wanted to make a 4 gs/s 12-or-so bit dac. You could make a circle of, say, 16 250 MHz dacs, which wouldn't be outrageously hard to feed, and then you'd have to generate a 16-phase clock to load them (from the equivalent of 16 fifo's) and then - the hard part - mux all of the analog outputs into a single summing point, one every 250 ps. The jitter and time alignment problem is identical, for the muxing process at least.

In my application, I'd like to be kicked off by an external trigger, so my clock must be externally startable too.

John

Interesting thread (I've read it all). I recall about eight years ago, a coworker was working on a digital RF receiver with a bandwidth of around maybe 50 to 70 MHZ. recall discussing the idea of using the ADC chips interleaved for higher bandwidth, and also that the data sheet saying interleaved used was not recommended (I don't remember the A/D chip used), but it didn't say why. Would anyone know why it would say this, other than the diffuculties already discussed in this thread?

"John Fields" schreef in bericht news: snipped-for-privacy@4ax.com...

If a particular single ADC chip with internal S/H can digitize a signal up to Nyquist, using your trick gives more datapoints. It will not allow you to digitize higher frequency signals reliably, but you will see a more accurate capturing of the waveform. To accomplish the same result with a single ADC, you would need a 10x faster one, under such circumstances.

So the trick is pretty useful, because not many applications using an ADC/SH actually go all the way up to the Nyquist limit anyway. You see this in oscilloscopes too, the cheap and famous TDS210 uses a single 1G/s ADC, but has a B/W of 60MHz. They could have used 10 x 120M/s ADC's too, of course, if they had found themselves in a time warp.

Perhaps we should say that the trick *was* pretty useful, on 1MHz ADC's because at those frequencies life is pretty simple. It's easy to see that trying to do the same with

Another thing we overlooked is that when we are victum of a backwards timewarp, we should realize that the desire to go 'back' may vanish instantly. If I was thrown back

"John Larkin" a écrit dans le message de news: snipped-for-privacy@4ax.com...

For this, you can (well I think, I've not gone too far into this) just sum all the ouputs and preprocess the digital datas to obtain the wanted output.

If that works, you owe me a coffee. Or maybe a beer.

The time-intereaved ADCs stink to high heaven. Analog Devices tried a hybrid of two of their meticulously trimmed 14-b 60MHz jobs to get a

Well quit chasing a dead end in that worthless time-interleaved scheme. The most promising ultra-high speed A/D architecture to date is the folding interpolating A/D scheme as instantiated here:

The scopes do it all the time. Some allow you 4 channels at x MHz, two channels at 2x MHz, and even sometimes one channel at 4x. I suspect the scopes are more concerned with visual quality and less with hard specs like sfdr and enob's and things.

Actually, "stacking" adc's can refer to stacking them in voltage, not time. The appnotes for some of the old true-flash adc's sometines suggested this... one adc would digitize from 1 to 2 volts, and the next one 2 to 3.

John

Hello John,

Just summing them would add all the glitch energies into the game which you probably don't want. That would require better than FET switches. I'd start out with fast diode bridges driven via inductive couplers. Making those couplers and preferably doing so with traces on the PCB is a true art. Ferrites aren't going to cut it up there.

Alternatively you could sum like Fred was suggesting but add a glitch energy muffler. Some of the hot rod SiGe transistors or at least a regular 9GHz version might be cool for that. What disturbs me a bit is that some SiGe is going lala-land. Philips has obsoleted their BFU510 and BFU540 after just a few years in the market. Over 30GHz fT in a SOT343 package for 50c. Can't even get a cup of decaf for that. Sigh. But there are others.

Ouch. Maybe a PLL with a 'sledge hammer phase reset'. Interesting project.

That'll be two beers :-)

Regards, Joerg

Hello John,

You could also run through an analog delay line, digitize before, feed back via a DAC into a subtract node after the line, then digitize again with another ADC that has an amp in front. Kind of 'stacking a few bits'.

Regards, Joerg

Hello Ben,

Maybe because the input circuitry and/or internal sampling stage didn't support much more bandwidth than that needed for its maximum conversion rate. However, you could still have interleaved them by providing your own faster sample/hold circuits for each converter on the outside. I have done that with lots of converters regardless of what the mfg thought about that.

Regards, Joerg

Hello Frank,

Headaches? Why? Dunnit a few times, didn't get a headache from it :-)

Regards, Joerg

Just summing wouldn't give the bandwidth I need, either. It's sort of the dual of the ADC problem: staggered adc's need fast s/h's, and staggered dacs need a fast gated multiplexer.

I was thinking diode current steering, maybe some 0.04 pF chip schottkies on a hybrid substrate. I know a guy who makes hybrids, and he owes me some favors.

I sort of know how to do that already (start an lc oscillator asynchronously, but phase-lock it to a good crystal clock) but I've only done that at 50 MHz or so. I'm thinking a triggereble coaxial ceramic resonator oscillator at 4 GHz as the starting point.

Any time. Alcohol lubricates brainstorming, up to a point at least.

John

"Joerg" schreef in bericht news:3hy_f.64516$ snipped-for-privacy@newssvr13.news.prodigy.com...

Yes, well, you have a better head than me. I would get headaches from hooking up a *single* 100 M/s ADC, let alone 10 of them ;)

Hello John,

Sure, you'd have to decouple from the DACs and do current summing or something like that. That should be possible with hotshot RF FETs in common base configuration, preferably the ones without protection diodes. With stripline and matched impedances it could possibly be done on a good FR4. Last time I looked at 5GHz telco stuff they had FR4 in there. Might have to be milled out under the diode.

Another option could be Pi-filter coupling. The DAC or transistor is the input capacitor and they'd all have a common output capacitor. Of course this would have to be nicely matched or it'll ring like crazy. Then there are hybrid couplers or even simple resistive combiners. In the microwave world they use these to combine dozens of channels.

I miss hybrids. Had done a few of them (thickfilm) but then the technology fell from grace and became expensive.

When you do that the LC would have to catch up to the phase of the crystal oscillator. The resonator sounds like a good idea. Something that acts like a pendulum, you let it go and it wants to stay at it's characteristic frequency and keeps going as long as energy is regularly replenished.

Gordon Biersch under the Bay Bridge used to be a good place. Except that it's kind of noisy in there.

Regards, Joerg

Seems it is new for

Thomas