ADC "stacking"

--- Generating multiple clocks and sampling the signal as it goes by in time doesn't involve the amplitude and temporal distortion which an analog delay line exhibits as functions of the frequency of the input signal or errors in the line itself.

Multiple clocks accurate to nanoseconds can easily be generated and used to sample the analog signal as it goes by, on the fly, without distorting it with a delay line.

There is shoot-through, but since it's only added to each of the separate signals sampled, it can be quantifed and removed once each sample is digitized.

-- John Fields Professional Circuit Designer

Thanks for your followup. I understand your scheme, but I still don't understand how, if the ADC's bandwidth (by which I meant the reciprocal of the duration of the analog sample-and-holding, not the sample rate) is only 1MHz, that any cascade of 10 of them as you describe can work.

Imagine a perfect 10MHz ADC sampling at 10MHz. At T=1 it converts X1, T=2 yields X2 and so on. A 1MHz bandwidth ADC @1MHz starts a conversion at T=10 and produces .1*(X1+X2+..X10). If you cascade 10 phase-shifted

So to clarify my original statement: If your ADC is sample rate limited, add more with clock delays, but if it's bandwidth limited, running two (or more) in parallel doesn't seem to buy you anything.

Hello Ben,

It does. But if the BW of your ADC is too low for the job you need to add a sample and hold before each ADC. No big deal, really. Had to do it many times because the ADC BW is indeed often lower than what's needed for the compounded solution. Other times it's high enough but the performance isn't quite up to par up there.

Regards, Joerg

--- Sorry, I didn't go into enough detail.

The scheme I described depends on the analog sample being acquired between the rising and falling edge of each phase clock and being held during the time the conversion is being performed, which starts with the falling edge of any phase clock and ends sometime before the next rising edge of that phase clock:

|---|D1 | DATA2>---|D2 | DATA3>---|D3 | DATA4>---|D4 | DATA5>---|D5 | DATA6>---|D6 | DATA7>---|D7 | DATA8>---|D8 | DATA9>---|D9 | +--------------+

with the relationshipbetween HFCK and the the phase clocks looking like this:

_ _ _ _ _ _ _ _ _ _ _ _ _ _ HFCK__|0|_|1|_|2|_|3|_|4|_|5|_|6|_|7|_|8|_|9|_|0|_| |_| |_| |_ ___ ___ PH0 __| |___________________________________| |___________ ___ PH1_______| |_______________________________________________ ___ PH2___________| |___________________________________________ ___ PH3_______________| |_______________________________________ ___ PH4___________________| |___________________________________ ___ PH5_______________________| |_______________________________ ___ PH6___________________________| |___________________________ ___ PH7_______________________________| |_______________________ ___ PH8___________________________________| |___________________ ___ PH9_______________________________________| |_______________

data will be presented to the muxer's inputs like this:

__ _______________________________________ _______________ D0 __|_______________________________________|_______________ _______ _______________________________________ ___________ D1 _______|_______________________________________|___________ ___________ _______________________________________ _______ D2 ___________|_______________________________________|_______ _______________ _______________________________________ ___ D3 _______________|_______________________________________|___ +__________________ _______________________________________ D4 ___________________|_______________________________________ _______________________ ___________________________________ D5 _______________________|___________________________________ ___________________________ _______________________________ D6 ___________________________|_______________________________ _______________________________ ___________________________ D7 _______________________________|___________________________ ___________________________________ _______________________ D8 ___________________________________|_______________________ _______________________________________ ___________________ D9 _______________________________________|___________________

but it'll come out like this:,

__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __ OUT __|___|___|___|___|___|___|___|___|___|___|___|___|___|__ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3

so your throughput has increased by a factor of 10!

-- John Fields Professional Circuit Designer

Nowadays, almost nobody sells s/h circuits, and you can't realistically make your own with sub-ns aperture time and reasonable accuracy. The best s/h circuits are inside the adc chips, integral to the design. At some point, the problem isn't so much the s/h or the adc, but delivering the flood of digital data into an affordable storage structure. One approach, like the scopes use, is to design an adc whose s/h has, say, 5 GHz analog bandwidth, and whose adc is a

Then you have the Joerg issue: the adc accuracy, and their clocks, have to be matched to absurd limits, and calibration becomes a very big deal.

John

In article , Tim Wescott wrote: [....]

How about this for a horrid way to "not use a charge pump":

Drive the gate of the JFET with one of those PV optoisolators. You can control the LED current to regulate the gate voltage.

This method is called "time-interleaved" A/D, not "stacking," and in most practical cases you end up with a hellacious mess of inharmonic and harmonic spurs way worse than the performance a component A/D would suggest, and because the application requires speed, this sort of implies significant analog input bandwidth making SFDR important.

Hello John,

You still can, done it many times. Some of them were blazingly fast, using inductive coupling and a quad diode switch. Can be done with two fast pairs since quads are had to come buy these days. Of course, for a sub-nsec sampling pulse you almost need the coax reflection trick. But every time I am contemplating that some new fast logic family comes to market.

Ye olde SD5400 was my favorite but it seems it's falling from grace. Expensive and harder to come by. Must be treated like ultra-thin china WRT to ESD.

Well, let's say I have often been mighty disappointed there. One issue is specsmanship. Most just give you a typical latency. But what's min and max? No entries, usually.

Regards, Joerg

Hello Fred,

Can't say that. I have done it many times and never really found anything hellacious in the data. Except where the client's engineers had insisted on split grounds around the ADCs, then it was truly hellacious. But easily fixed by a lil' copper pour.

Regards, Joerg

That you can't realistically use a separate s/h and adc, and that the sh/adc combo chip must be an unusual beast, with a s/h bandwidth

Your approach? Did you invent interleaving adc's?

I just mentioned a few facts and issues about the difficulty of interleaving adc's. I didn't make any personal statements at all, until just now.

If one doesn't handle it right - sufficient s/h bandwidth, properly aligned clocks, very tightly matched adc performance, probably a lot of digital data tweaking, very fancy calibration algorithms - using a lot of adc's may well be worse then using one and interpolating data points to make it look like more.

John

In article , Joerg wrote: [....]

I get my members of that club from

On this and many specs like it, the typical isn't the middle of the band.

I think cool circuits are cool, no matter who invented them.

If you're going to make every technical discussion a battle over your personal validity, well, best of luck.

John

Hello Ken,

You still can get similar chips but let's face it, they seem to become boutique parts. I started to retreat when the prices climbed. The good thing is that PIN diodes are now quite favorable in pricing. Unfortunately they aren't suited too well to clock skewing.

Yes, I am painfully aware of the first time I ran into this. Luckily I had plenty of adjustment range. The problem is serious when interleaved ADCs aren't all from the same lot.

Regards, Joerg

Well, of course. That's the way people are. And naturally, if I invent something, even if it's not original to the world, it is novel to me, so it gets my interest. But when one of my guys invents something clever, and they do, and it's better than my ideas, which is often is, I'm delighted.

What's dangerous, and I see it too often, is when a person falls in love with his own flawed idea, and pursues it in the face of reason.

And all I did was comment on some of the details. I didn't say anything personal about you.

Reread the threads. I said nothing of the sort, and said nothing personal. It's obviously neither unworkable nor stupid, since Tek and Agilent and LeCroy make megabucks off interleaved ADCs. It *is* difficult, and just adding interleaved adc's doesn't automatically add bandwidth or signal quality. Ask Joerg, who knows more about this than either of us.

Feel free to ignore my opions. Also feel free to view them as personal attacks on you, even though they aren't. It's only a newsgroup.

John