A2Ds S/H times vs LSB noise

If I understood your setup right then, yes. Larger cap -> longer integration time -> slower system -> less noise.

This is true in the general; however there are also the leakage effects and the noise.

The internal ADC of F2812 is really lousy. It is probably the worst in its kind. The accuracy is poor, the self noise is high, and the internal voltage reference is crap. The increased S/H time is not going to help. What you can do is averaging many samples; this will reduce the noise as the square root of the number of samples. Also, make sure that the ADC clock is in the integer ratio with all other system clocks.

That ADC is very bad by itself.

Not really.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

This is good input. We are this in the EZDSP which is setup to use the internal voltage references. When you say the internal references are bad are you saying that they are inaccurate (I know the 1V difference between the two voltage references is not that great which should affect scale but not noise.

Hmmm. Looks like I'll have to run a test with the A2Ds connected diretly to the 1V reference and see what the noise looks like. Should be almost zero but I bet it isn't.

The noise level did get a little lower when I placed a .1uF ceramic cap from input to ground (luckly the opamp didn't oscillate). That usually really gets it.

I guess I could acquire 100 crappy samples at 80nS and then average them in the same amount of time.

Better solution?

Some 2^N value for the number (64, 128) of samples, then an arithmetic shift does the divide.

But bottomline you have to try it out. Sometimes averaging helps a lot, sometimes you need to lowpass or pre-sample the input, sometimes both. It all depends on where noise gets in and how much. For example, if the ground is bouncing about then averaging might not do much.

Averaging helps with the noise, however it can't help with the accuracy. The ADC of 2812 has to be calibrated for the offset and scale factor. Otherwise it will be accurate only to 1% or so.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

Yeah, so far I have been less than enthused with on-chip converters. Delicate analog circuitry and fast digital stuff don't mix well.

Same for delicate analog stuff together with power devices. I received a hard dose of reality regarding that one last week, or rather, a client of mine did. It kind of hurt when I had to break that news to them (means a redesign). It was almost like telling your neighbor that the garbage truck had just crunched their vintage car.

Luckly for us we are driving a BLDC motor with it so the noise is not THAT big of an issue. But I wanted to get it down to within reason.

We got the noise down to about +/- 10mV (converted answer) by adding a .1uF x7r cap right across the input and increasing the S/H window to 10uS. Still pretty bad but livable.

So whats that about 7-8 bits? :\\

Might try a FIR in the input sampled if the delay isn't too bad and there is time at the end of the project. This should clean up the signals that are monitored by the user (bus voltage, bus current, RMS phase current amplitude, etc)

Thanks for the input guys.

My suggestion was about simplifying the mathemtical algorithms for computational speed. Not a big deal today for desktop machines, but could be important for embedded systems.

Yes, I'm and keeping your average 2^n suggestion under consideration. I can get 64 samples and average in 10us. We'll see if that is better than the current solution.