Added a trimmer to set f0, the advantage is that it is voltage independent, and you can set f0 as close as you want to the wanted frequency, this allows for a small loop bandwidth, and reduces noise. Also note that now its running on (stabilized by LM317) 3.3V, this requires some more capacitance than you can get by driving BC584B towards low VCE (remember higher voltage = lower frequency). So the capacitor was needed anyways, this one came from an old remote:
Those interested in the values of the loop filter should ask here.
+3.3 | | [ ] 680 25M | ----|[]|--- | | 100k |--------------------> out | ---===-----| c | \ 100k | |/ |/ 5.6 - 100 pF trimmer -----===--------------| BC548B === control- |\/ e /| voltage | | /// ///
I managed to get 3 DLL frequency doublers working in series in the spartan2 FPGA, this gives 8 x 25MHz = 200MHz, back to the original design resolutions. Just cannot get these things out of lock it seems. This is 10MHz rubidium reference against 50MHz (after first doubler):
Now this 200MHz is used to make all sorts of frequencies, one of those is GPS L1 / 256 (prescaler):
Amazing is that I synthesized this all with an old Xilinx xst webpack. Ran out of global clock buffers BUFG, that gives me only one warning. Not using that GUI, just scripts in Linux, really fast, not so fast is all the errors of their soft you have to look up on the web to fix or work around. Hey, but its working :-)