A simple tunable crystal oscillator

build in thing in the Spartan2 FPGA)

turning a potmeter,

voltage.

Nice, thanks for posting this.

If you want a commercial product with 50ps p-p jitter spec, the 3.3V Pericom FRETHE025 is not too pricey and has a similar range (+/-100ppm for 0.3 to 3V control voltage).

build in thing in the Spartan2 FPGA)

One caution: the Spartan 2 DLL, used as a doubler, will make a slightly lopsided

build in thing in the Spartan2 FPGA)

by turning a potmeter,

voltage.

That's pretty cool. What would you do to make this run with less than

Rick

You might want to analyze the snot out of it before you trust it to always work in a production application (Jan's oscillator, not the Pericom).

I suspect that the current is going to vary a lot with the control voltage.

I dimly remember that you can use the B-C junction of a transistor for a varicap, but I've never tried it. Just using a regular crystal with a transistor "varicap" may work better, and if it does it should give you a better opportunity to keep the current down.

BTW: if this is for your WWBV receiver then you can probably do a lot better by having a free-running crystal oscillator and dividing it down with a dithered divide ratio to get 240kHz.

For example, if you use your cited 4MHz crystal and divide by 16 or 17, correctly dithered, then you'll have whatever average frequency you want between 235 and 250kHz, and your sampling instant will never be more than

build in thing in the Spartan2 FPGA)

by turning a potmeter,

voltage.

You might need to change the transistor to a BFR92

or something with an even lower collector-base capacitance. Just charging up the 0.75pF of the BFR92 to 1.8V four millions times a second would use up 5uA.

Tim Wesnott:

I prefer reality over your limited mathematical models.

Okay, test the snot out of it. ;-)

build in thing in the Spartan2 FPGA)

That's SO twisted! Your FPGA will want square wave input, and it has onboard clocked logic (which will skew the results from the 'locked loop').

Rather, just use a Schmitt trigger to make sure of good square waves, and filter (LC tuned filter) the fifth harmonic. From 10 MHz out to 50 MHz, it shouldn't take (or depend on) all the jitter you'd get from a clocked FPGA. Optionally, a second Schmitt trigger will square up the sinewaves from your filter...

...snip...

Yes, this is for the WWVB receiver. I can't say I follow why a fixed frequency XO would be better. Are you saying it could be lower power? Right now the problem is that I haven't found anything with a low enough power spec XO or VCO. I thought I had found some very low power oscillators a few months ago, but I can't find any notes or links.

A fixed rate oscillator would have to run a lot faster than 4 MHz because that is the sample rate of the sigma delta input. The output sample rate is 240 kHz. I suppose it could be used with a variable sigma delta integration period to do the dithering though. This is not an attempt to build a high fidelity receiver, so I expect any perturbations from the dithered integration period would not be important.

I've been thinking about the ADC a bit and I've never been convinced that the "poor man's" sigma delta (no noise dithering and no filtering) is a lot better than just using the differential input directly with the antenna input. That even gets rid of the loop and RC time constant. Use the differential input as a true 1 bit DAC. Depending on how well the rest of the processing works it might do ok sampling at 240 kHz directly.

Rick

Digikey has several types of 60 KHz tuning fork crystals which can be useful to filter out the noise, if all you want is the 60 KHz carrier. Divide by three, the two to get a clean 10 KHz, and a PLL to get whatever frequency you want.

On a sunny day (Wed, 5 Dec 2012 11:44:44 -0800 (PST)) it happened whit3rd wrote in :

build in thing in the Spartan2 FPGA)

Actually I have been playing a bit today with 2x multipliers and LC at 25->50MHz the inductors and c become small, you need extra gain.. 3 stages at least to make a good square wave. Tried 2 phase rectifier doubler too, several configurations.. Bit of a revival from the old days when I build radio receivers and transmitters. I want to be able to be independent of the rubitin reference, so just tune the crystal. Did some measurements today, connected the FPGA board... The alternative is to tune a 50MHz crystal, plenty on ebay for peanuts.

Jitter... there are several PLL loops in this, and several clock multipliers... To boldly go where...

The GHz loop locks just like ZAP, and seems very stable, PLL 2 pole xor detector at about 6 MHz, fractional divider in FPGA. Not in a hurry, its a table full of logic now...

a build in thing in the Spartan2 FPGA)

by turning a potmeter,

voltage.

I was starting to do a little digging on the transistor and Firefox crashed. I always have a bazillion tabs open using all my memory so every once in awhile it does this. I see what you mean about the capacitance. I remember one of the articles I had found reported some 5 or 10 pF on the output and most of the circuit power was used charging and discharging that to 3.3 volts.

This is on my list of things I still need to research.

Rick

Thanks for the idea. I am trying to do as much as possible in the FPGA with as little power as possible. I haven't seen many PLLs that are very low power. Of course I could do that in the FPGA as well. I'm pretty sure the filtering would work better digitally. But we'll see!

Actually, I just had a thought. If it is going to use double digit uAs to bring a ~4 MHz clock onto the chip because of the I/O capacitance, maybe I should use a lower frequency reference with the internal oscillator. I don't know how much power it uses, but it should be stable enough to allow periodic frequency calibration to a low frequency reference.

Like I said, I haven't had a chance to spend a lot of time on this part of the design yet.

Rick

A passive crystal filter doesn't need power. and the crystals are cheap.

I'm not really familiar with that type of circuit. Do you think it will have a higher Q than the antenna tuned circuit? I expect that to have a Q of nearly 100. The last calculation I've done which includes the inductor self capacitance is 89. Does the crystal require any buffering? I'm not planning to use a preamp of any sort and the receiver has to present a very high impedance to the antenna to prevent loading and reduction of the Q. I don't recall the value I've calculated, but I believe it needs to be in the range of Mohms.

I guess I could look up some references. Maybe tomorrow.

Rick

Be sure to make up enough different units, with verified component values, so that that you know you've at least hit all of the vertexes of the parameter variation space, and test all of them over your entire temperature range.

Try a BFG25A/X. It's like a BFT25A on steroids--a very small die and pretty fast. (You can get 110 GHz f_max packaged transistors nowadays, so it's nowhere near being a speed champion, but it stays fast at pretty low I_C.)

Cheers

Phil Hobbs