A less squirrely cute little circuit

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I started off with a simulation of the original cute circuit, which was posted to the original "A cute little circuit" thread, and I did enough work on that circuit to know that I didn't like it much - with the results that I also posted to the original thread.

The circuit that I've posted here strikes me as a easier to tame, on the basis of the simulations I've run. The simulations aren't to be trusted, but I'm not going to go to the trouble of getting the parts that Tim Williams chose or winding the toroids so that I can test a real circuit - the work would be out of proportion to the reward.

How? I presume that you are setting the initial voltage on one of the nodes of the circuit, but which one?

Such a difference to what? Please try to be explicit and specific.

The simulation isn't trickery or sleight-of-hand. I've posted exactly what I simulated, and if you run that circuit in your version of LTSpice you should see exactly what I saw.

If you can get a slightly - and interestingly - different version of this circuit to oscillate at a few MHz rather than a hundred or so kHz, post it so we can see what's going on.

For me, the crucial change to Tim's original circuit was the addition of the ferrite beads L9 and L10 to the output rectifier, which was enough to stop the original circuit from oscillating at 8MHz. If your circuit has reverted to that behaviour, you may need current limiting resistors or bigger inductors at L9 and L10.

Simulation is a cheap and quick way of doing "what-if" experiments. It's no substitute for building a testing a real circuit, but it can be a cheap way of showing bad ideas.

-- Bill Sloman, Nijmegen

I've seen no tendancy towards this behavior. I don't see how that would cause a problem, the 1.4V of off-state slop is plenty to generate a small signal oscillation. As the oscillation grows, it bangs into the diodes, and starts generating power. No quenching. Perhaps the 1N914 model has too much CJO or TT or something?

I have in fact observed squigglies in the MHz, which the 0.0022 flattened more or less, at least under normal operation (as opposed to the squeggy operation the original circuit exhibits at low current). Some strategically placed FBs should eliminate that.

It's a toroid, but the permeability is a little low; I'd guess k = 0.995, and maybe 0.95 for the base winding.

Cite? I don't recall seeing tabulated reverse beta in, for instance, AoE2.

If you mean general advice, that doesn't count: I've measured betas from 0.2 to 100.

Not worth it- no manufacturers offer a realistic model anyway. I haven't even seen one which models the REF input pin leakage and clamp diodes. Never seen one which compensates realistically either; SPICE might tell me it's a stable circuit with 220k + 100pF feedback, whereas reality ends up with a more typical 10k + 10n or so. Pretty gross.

And for higher voltages, you use clamp diodes, so the opposing drain pulls down the gate, but it only rises back up to the gate supply voltage. I've done that, with a highspeed diode, moderate pullup, and gate driver for extra speed. 1MHz easy.

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms

I'm all for lateral thinking. It gets the job done and circumvents unnecessary delays.

It's necessary to 'keep your eye on the prize'. In this case, I thought it was not the aim to make just any simulation, but a simulation of the original circuit that was claimed to work. The 'cute' one. If this is not the dase, my interest ends here.

In cute1var3.asc, there is only one varying source. Setting it's starting voltage 400mV higher seemed to spark the familiar HF oscillation mode.

I thoght I'd documented and saved this, but apparently the iteration was over-written. I succeeded (somehow) in getting this to run normally. I don't know how.(!!!!) Probably altered some completely irrelevent thing like the number of digits in the data collction starting time.

You've got no argument here. The 'what if' has greater impact if the original complies to what's been built, to start with, though.

. d

, and

too

It doesn't have any inductance, and inch of wire has an inductance of

10nH. There will be more than that in the real circuit - maybe enough prevent the behaviour. There's also the series resistance of the reservoir capacitors.

Bunging in the ferrite beads was quicker tha moaking the models more realistic, and they help minimise RFI problems in real circuits.

cally

5,

oE2.

My copy of AoE is already in Australia, but IIRR nobody tabulates reverse beta, but IIRR pretty much everybody used to point out that the design of the base junction to get good forward beta almost always gives you a reverse beta in the 1 to 2 range.

This goes back to the late 1970's when I was using inverted transistors a low-offset saturating switches, so there may have been some bit-rot in my memory.

=20 (reverse?)

from 0.2

I find that a bit surprising. Maybe someone will tell us exactly what's going on ...

TI less than most. Their marketing department seems to think that engineers should be impressed by data, rather than informed. They don't seem to think about repeat sales.

e

Nobody much models the stray inductances,capacitances and ground return impedances around their circuits either

s

've

I'm only aware of it as theoretical possibility - they looks good in simulations, but most of my work on inverters preceded really cheap MOSFETs.

-- Bill Sloman, Nijmegen

On 8/3/2012 12:54 AM, Tim Williams wrote:

Here's a LTSpice transcription of the circuit, plus the modifications that gave me more or less respectable performance in simulation.

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WINDOW 0 36 80 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName L4 SYMATTR Value 4µ SYMATTR Type ind SYMATTR SpiceLine Rser=0.1 Cpar=1p SYMBOL polcap -160 -672 R0 WINDOW 3 24 56 Left 2 SYMATTR Value 47µ SYMATTR InstName C6 SYMATTR Description Capacitor SYMATTR Type cap SYMATTR SpiceLine V=4 Irms=0 Rser=2.4 Lser=0 mfg="AVX" pn="TAJB476M004" type="Tantalum" SYMBOL References\\LT1431 -1568 464 R0 SYMATTR InstName U1 SYMBOL res -976 -656 R0 SYMATTR InstName R2 SYMATTR Value 4.7k SYMBOL res -976 480 R0 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL cap -1408 240 R0 SYMATTR InstName C7 SYMATTR Value 100n SYMBOL res -1760 -224 R0 SYMATTR InstName R6 SYMATTR Value 1k SYMBOL res -1408 128 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 47k SYMBOL voltage -2144 0 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value 9 SYMBOL FerriteBead -2064 -720 R90 WINDOW 0 -16 0 VBottom 2 SYMATTR InstName L7 SYMATTR Value 3.642µ SYMATTR SpiceLine Ipk=0.2 Rser=0.6 Rpar=2700 Cpar=1.122p mfg="Wurth Elektronik" pn="742 792 092" SYMBOL FerriteBead 0 448 R180 SYMATTR InstName L9 SYMATTR Value 3.642µ SYMATTR SpiceLine Ipk=0.2 Rser=0.6 Rpar=2700 Cpar=1.122p mfg="Wurth Elektronik" pn="742 792 092" SYMBOL FerriteBead 64 -400 R270 WINDOW 0 16 0 VTop 2 SYMATTR InstName L10 SYMATTR Value 3.642µ SYMATTR SpiceLine Ipk=0.2 Rser=0.6 Rpar=2700 Cpar=1.122p mfg="Wurth Elektronik" pn="742 792 092" SYMBOL FerriteBead -2000 -768 R90 WINDOW 0 -16 0 VBottom 2 SYMATTR InstName L13 SYMATTR Value 3.642µ SYMATTR SpiceLine Ipk=0.2 Rser=0.6 Rpar=2700 Cpar=1.122p mfg="Wurth Elektronik" pn="742 792 092" SYMBOL polcap -864 -688 R0 WINDOW 3 24 56 Left 2 SYMATTR Value 1µ SYMATTR InstName C9 SYMATTR Description Capacitor SYMATTR Type cap SYMATTR SpiceLine V=16 Irms=0 Rser=11 Lser=0 mfg="AVX" pn="TAJA105K016" type="Tantalum" SYMBOL cap -224 -672 R0 SYMATTR InstName C12 SYMATTR Value 100n SYMBOL npn -1888 240 M0 SYMATTR InstName Q3 SYMATTR Value 2N4401 SYMBOL res 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IRB=2.41268 RBM=0.218936\n+RE=0.0152284 RC=0.0761421 XTB=0.1 XTI=1\n+EG=1.05 CJE=3.26474e-10 VJE=0.446178 MJE=0.464223\n+TF=1e-08 XTF=3.50642 VTF=8.2848 ITF=0.0305862\n+CJC=3.07595e-10 VJC=0.77548 MJC=0.476497 XCJC=0.799334\n+FC=0.8 CJS=0 VJS=0.75 MJS=0.5\n+TR=9.57121e-06 PTF=0 KF=0 AF=1\n* Model generated on Feb 8,

2004\n* Model format: PSpice

I've added a 43k load resistor at R12 to soak up the 3ma that Tim wants the circuit to supply.

To get the circuit to behave itself, I've added C8 and C10 and increased C7 to 100n. That keeps the ripple at the REF input down to 8mV peak to peak. There's still 63mV ripple across C10 and R10, which shows up as

8mA ripple on the 80mA of current through Q4.

One could do more, but you'd want to know more about how the circuit was going to be used before you started doing any fine tuning.

I've e-mailed Tim a screen shot and the Spice netlist.

--
Bill Sloman, Nijmegen

Oh, so they aren't real ferrite beads (at least, not "real life" sized ones!), just a dab of inductance?

I think the FB models in Multisim's library are RLC equivalents.

Concerning parasitics in general, I don't like that about LTSpice: I don't have a clue what RS, LS you may've specified for C6, 9, 11, 12, or V1 for that matter. I'd have to, gasp, trudge through the .ASC (or download a program to read it!).

I'm surprised the LL of the transformer doesn't do it already, guess it's a symptom of the C2-diodes-C3-C4 loop.

Probably a 1m resistor would do as well. 10n will be nicely representative of the real world, though it shouldn't do much given the low currents. Won't do much for stability either, of course; an R || L (like... a ferrite bead!) does wonders for stability and reality, though.

If nothing else, the SPICE model shows BR=0.1 (beta, reversed). Under what assumptions is going to depend on the model (Gummel-Poon I believe?). I don't believe BF=134 very much either, though models tend to be optimistic on beta anyway (often using the max or high-temp value, rather than min or typical).

I've got a few of these floating around, pulled from stereos:

I suppose epitaxial is more likely than double or triple diffused types for parameters like these. Hearkens back to the days of germanium -- who cares which lead you pick for collector or emitter, they're the same anyway!

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms

Thanks. Doesn't look like much changed, I'm a bit surprised how many caps got added to it though. C10 I guess is more for bypassing B-C capacitance? C8 is unusual, and "shouldn't" do much, at least that can't be accomplished by reducing R7 or what have you.

Tim

-- Deep Friar: a very philos>>>> Inductance is a bit low, FT50-43 with 15 turns should be more like

No, they are real life ferrite beads - Wurth 742 792 092 - 3.6uH,

0.6R, 1.1p with a maximum high frequency impedance of about 2k at 80MHz.

I've just bought a bunch of them for my low distortion oscillator.

t

It's all available if you load the .asc file into a copy of LTSpice - you cn read the library Spice model files.

a

tive

te

r what

I

tic

r

=A0 betas

or

ares

Before my time. But most FETs are genuinely symmetrical if you want a more relevant example.

-- Bill Sloman, Nijmegen

The behaviour changed quite a bit.

There's quite a lot of ripple on the current coming out of Q3. C10 means that there's less of it getting into the base of Q4. I'm thinking about adding another RC or RLC bypass between Q3 and the base of Q4.

ed

C8 is crucial to reducing the ripple on the current coming out of Q3, and thus the ripple on the REF input to the LT1431 - I've got ti down to 8mV peak to peak, which isn't that far below the 50mV level where the non-linearity of a bipolar long-tailed pair input starts getting embarrasing.

Bill Sloman, Nijmegen

On 8/4/2012 11:20 AM, Bill Sloman wrote:

I tried it, and it didn't seen to do anything useful

I've had another go at the circuit, and got rid of or reduced a couple of capacitors that didn't seem to be doing anything useful and added a new one - C2, 330pF - between the centre-tap of the base driven winding and ground, which adds a bit of break-before-make character to the inverter switches. It doesn't do much, but I figure that it's an interesting and not-all-that-obvious idea.

The inverter runs a bit faster, but seems to do much the same job.

Compared with the emitter-follower variation, it's probably a bit cheaper to put together, but a worse source of electromagnetic interference.

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WIRE -1104 640 -1216 640 WIRE -960 640 -960 576 WIRE -960 640 -1104 640 WIRE -640 640 -640 320 WIRE -640 640 -960 640 WIRE -80 640 -640 640 WIRE 0 640 0 480 WIRE 0 640 -80 640 WIRE 128 640 128 288 WIRE 128 640 0 640 WIRE 208 640 208 80 WIRE 208 640 128 640 WIRE 336 640 336 592 WIRE 336 640 208 640 WIRE 464 640 464 96 WIRE 464 640 336 640 WIRE -80 688 -80 640 FLAG -80 688 0 FLAG -144 -256 0 SYMBOL npn -704 192 R0 SYMATTR InstName Q1 SYMATTR Value 2N4401 SYMBOL npn -864 -80 R0 SYMATTR InstName Q2 SYMATTR Value 2N4401 SYMBOL ind2 -432 -112 R0 SYMATTR InstName L1 SYMATTR Value 44µ SYMATTR Type ind SYMATTR SpiceLine Rser=0.1 Cpar=1p SYMBOL ind2 -432 32 R0 SYMATTR InstName L2 SYMATTR Value 44µ SYMATTR Type ind SYMATTR SpiceLine Rser=0.1 Cpar=1p SYMBOL cap -656 -16 R0 SYMATTR InstName C1 SYMATTR Value 100p SYMBOL ind2 -256 -64 R0 SYMATTR InstName L5 SYMATTR Value 4.4m SYMATTR Type ind SYMATTR SpiceLine Rser=0.1 Cpar=1p SYMBOL diode 16 -144 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D1 SYMATTR Value 1N914 SYMBOL diode 16 -256 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D2 SYMATTR Value 1N914 SYMBOL diode 16 224 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D3 SYMATTR Value 1N914 SYMBOL diode 16 320 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D4 SYMATTR Value 1N914 SYMBOL cap 96 -272 R0 SYMATTR InstName C3 SYMATTR Value 6.8n SYMBOL cap 112 224 R0 SYMATTR InstName C4 SYMATTR Value 6.8n SYMBOL cap 192 16 R0 SYMATTR InstName C5 SYMATTR Value 100n SYMBOL res 320 -320 R0 SYMATTR InstName R1 SYMATTR Value 1000k SYMBOL res 320 256 R0 SYMATTR InstName P1a SYMATTR Value 5k SYMBOL res 320 384 R0 SYMATTR InstName P1b SYMATTR Value 5k SYMBOL res 320 496 R0 SYMATTR InstName R4 SYMATTR Value 15k SYMBOL ind2 -1008 96 R180 WINDOW 0 36 80 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName L3 SYMATTR Value 4µ SYMATTR Type ind SYMATTR SpiceLine Rser=0.1 Cpar=1p SYMBOL ind2 -1008 240 R180 WINDOW 0 36 80 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName L4 SYMATTR Value 4µ SYMATTR Type ind SYMATTR SpiceLine Rser=0.1 Cpar=1p SYMBOL polcap -160 -672 R0 WINDOW 3 24 56 Left 2 SYMATTR Value 47µ SYMATTR InstName C6 SYMATTR Description Capacitor SYMATTR Type cap SYMATTR SpiceLine V=4 Irms=0 Rser=2.4 Lser=0 mfg="AVX" pn="TAJB476M004" type="Tantalum" SYMBOL References\\LT1431 -1568 464 R0 SYMATTR InstName U1 SYMBOL res -976 -656 R0 SYMATTR InstName R2 SYMATTR Value 4.7k SYMBOL res -976 480 R0 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL cap -1408 240 R0 SYMATTR InstName C7 SYMATTR Value 100n SYMBOL res -1760 -224 R0 SYMATTR InstName R6 SYMATTR Value 1k SYMBOL res -1408 128 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 47k SYMBOL voltage -2144 0 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value 9 SYMBOL FerriteBead -2064 -720 R90 WINDOW 0 -16 0 VBottom 2 SYMATTR InstName L7 SYMATTR Value 3.642µ SYMATTR SpiceLine Ipk=0.2 Rser=0.6 Rpar=2700 Cpar=1.122p mfg="Wurth Elektronik" pn="742 792 092" SYMBOL FerriteBead 0 448 R180 SYMATTR InstName L9 SYMATTR Value 3.642µ SYMATTR SpiceLine Ipk=0.2 Rser=0.6 Rpar=2700 Cpar=1.122p mfg="Wurth Elektronik" pn="742 792 092" SYMBOL FerriteBead 64 -400 R270 WINDOW 0 16 0 VTop 2 SYMATTR InstName L10 SYMATTR Value 3.642µ SYMATTR SpiceLine Ipk=0.2 Rser=0.6 Rpar=2700 Cpar=1.122p mfg="Wurth Elektronik" pn="742 792 092" SYMBOL FerriteBead -2000 -768 R90 WINDOW 0 -16 0 VBottom 2 SYMATTR InstName L13 SYMATTR Value 3.642µ SYMATTR SpiceLine Ipk=0.2 Rser=0.6 Rpar=2700 Cpar=1.122p mfg="Wurth Elektronik" pn="742 792 092" SYMBOL polcap -864 -688 R0 WINDOW 3 24 56 Left 2 SYMATTR Value 1µ SYMATTR InstName C9 SYMATTR Description Capacitor SYMATTR Type cap SYMATTR SpiceLine V=16 Irms=0 Rser=11 Lser=0 mfg="AVX" pn="TAJA105K016" type="Tantalum" SYMBOL cap -224 -672 R0 SYMATTR InstName C12 SYMATTR Value 100n SYMBOL npn -1888 240 M0 SYMATTR InstName Q3 SYMATTR Value 2N4401 SYMBOL res -1840 48 R0 SYMATTR InstName R5 SYMATTR Value 10k SYMBOL res -1840 416 R0 SYMATTR InstName R8 SYMATTR Value 10k SYMBOL res -1968 432 R0 SYMATTR InstName R9 SYMATTR Value 390 SYMBOL res -1968 -672 R0 SYMATTR InstName R10 SYMATTR Value 220 SYMBOL res -528 -704 R0 SYMATTR InstName R11 SYMATTR Value 10 SYMBOL pnp -576 -368 M180 SYMATTR InstName Q4 SYMATTR Value TIP32 SYMBOL cap -1232 240 R0 SYMATTR InstName C8 SYMATTR Value 100n SYMBOL cap -1584 -640 R0 SYMATTR InstName C10 SYMATTR Value 100n SYMBOL res 448 0 R0 SYMATTR InstName R12 SYMATTR Value 43k SYMBOL cap -752 -672 R0 SYMATTR InstName C11 SYMATTR Value 100n SYMBOL cap -1120 512 R0 SYMATTR InstName C2 SYMATTR Value 330p TEXT -496 224 Left 2 !K1 L1 L2 L3 L4 L5 0.999 TEXT -312 -24 Left 2 ;| TEXT -312 0 Left 2 ;| TEXT -328 -24 Left 2 ;| TEXT -328 0 Left 2 ;| TEXT -1592 688 Left 2 !.tran 0 20m 0 10n startup TEXT -1672 -360 Left 2 !.MODEL tip32 pnp\n+IS=1e-09 BF=134.366 NF=1.29961 VAF=10\n+IKF=0.742988 ISE=1e-16 NE=1.40014 BR=0.1\n+NR=1.46599 VAR=100 IKR=3.21978 ISC=1e-16\n+NC=2.71657 RB=7.44433 IRB=2.41268 RBM=0.218936\n+RE=0.0152284 RC=0.0761421 XTB=0.1 XTI=1\n+EG=1.05 CJE=3.26474e-10 VJE=0.446178 MJE=0.464223\n+TF=1e-08 XTF=3.50642 VTF=8.2848 ITF=0.0305862\n+CJC=3.07595e-10 VJC=0.77548 MJC=0.476497 XCJC=0.799334\n+FC=0.8 CJS=0 VJS=0.75 MJS=0.5\n+TR=9.57121e-06 PTF=0 KF=0 AF=1\n* Model generated on Feb 8,

2004\n* Model format: PSpice

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Bill Sloman, Nijmegen