82C55A

Thanks. What about a CPLD? I saw on 8052.com some designers had done this. I only use Mode0/Word8 and Mode0/Word12 combinations (need 1 bit of port C as input on occasion). So this could be done discretely but I don't think I have the area for a '244, and '374 for A and B which are always the same and a 74HC646 for C plus the decoding logic (a '138 I guess). So I wonder if a CPLD in PLCC format could work without an artwork change? I've not overly experienced in CPLD designs and the bus part seems the trickiest but decoding A0 and A1 (lower address latched via '373 on my design) would be easy and creating 9 inputs and

The original 82c55 resets to 1, weak pullups, ports as inputs. The OKI part never was a drop in replacement for the original Intel part.

Time for a redesign.

Reset clears the register contents in the Mitsubishi and Toshiba parts, according to their datasheets. Everyone's 82c55 goes to high-Z input mode.

Check this out:

Here's a quote: "But beware of the 'improved' Intersil 82C55A. That one still does the 'design feature' but also has inbuilt active pullups that are ON at POR/Reset."

I think the Intersil "bus hold devices" are indeed a bit different than the dare I say standard 82c55a.

Thanks!

On 17/12/2005 the venerable snipped-for-privacy@revco.spx.com etched in runes:

Since the Intersil part uses weak pull-ups internally, couldn't you just put some stronger pull-downs on the output?

I've done this with a small Altera max part. I didnt implement the entire 8255, just what I needed. Bus connection is easy. Dont forget its a 150ns part your desiging.

Power pins will be where you dont want them. And the package may not be what you want.

Cheers

You don't need a part that resets to zero. You tell us why that part has to reset to zero. The Intersil part is better.

The o/p polarity at POR is not the whole problem Fred.

The original NMOS 8255A (and 8255A-5) set all 24 i/o to inputs at POR. That's the safe thing for an i/o device to do and (afair) there were no internal pullup/downs, so you could use external resistors to choose the safe POR state for any i/o lines that were going to be outputs. ........... or so you thought initially

Because the 8255A had a design feature, which was quite an ambush. From my 1979 data book.. "All of the output registers, including the status flipflops will be reset whenever the Mode is changed."

So you could only use pulldowns to set the POR polarity, and had to adjust the following hardware to suit a logic 0 default polarity. Then along came the CMOS versions, each with their own design features.

The OKI 82C55A-2 is more or less a compatible replacement for the NMOS 8255. However the OKI 82C55A-5, on a Mode change, still sets all outputs on Ports A and C to zero, but now leaves Port B outputs undefined.

The Intersil 82C55A introduced a new wrinkle. They added a feature called 'bus hold', which is internal pullup/downs.

At POR all i/o is set to inputs, but now with a 400uA pullup.

However the silly B's still kept the feature that any Mode change then slapped all outputs to a logic 0.

To get the same POR and Mode change polarities with the Intersil 82C55A all outputs should have pulldowns, value not greater than about 2k.

Also, the OKI parts, you cannot read the status register, like the origninal Intel part.

Cheers

Intel part.

Opps, I meant the mode register.

I found some other potential Intersil drop-ins w/out the bus hold feature.

CMS82C55AZ IMS82C55AZ

I have these on the way for test. The features area even mentions the OKI part. Here's a link to the spec:

Thanks!

Good find.