320pin BGA Pin Layout suggestions

Hi All,

I am looing at laying out 320pin BGA on a PCB like this one.

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The pitch between balls is 0.5mm. The internal cpu speed is 220MHz but the external I think is ~60MHz.

It has a JTAG port

Questions Q1 How many PCB layers would you recommend and why

Q2 Is there anything else I should watch out for?

Any other pointers on this beast would be appreciated.

Regards Joseph

Reply to
Joe G (Home)
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Might depend on (among other things) how many of those 320 pins you are actually using. I had to use a 900+pin BGA package once but only needed a few dozen I/ O. You are lucky with that arrangement in that you have plenty of space in the middle of the device for breaking out the inner pins. With any luck you won't need two traces between any of the pads.

4 layer bare minimum of course depending on pin usage, with 6 or 8 layers being more likely and this will give you a lot more route and power options.

Power decoupling and power plane usage. Follow the manufacturers recommended guidelines precisely.

Dave.

Reply to
David L. Jones

Not enough information. The BGA looks fairly simple (only four rings) but I'd need to know what the power balls look like and how many supplies. If it's only a single supply and the inner balls are only power (often the case) you can get by with four layers (2S2P). I'd add another plane if I/Os are on the inner ring and one for other supplies.

As David indicated, decoupling caps.that square in the middle of the BGA is a perfect place for them.

--
  Keith
Reply to
krw

.5MM BGAs tend to be a whole new ball game. From .75mm pitch on up you can do a conventional "Dog Bone" approach to fanning them out. For .5mm the drill/pad/land size is not manufacuturable for Dog Bone fan outs. So you need to do Via in a Pad. Step one, then is to make sure your PCB vendor can do via in a pad (with plug and fill of course). That said you "may" not have to do that for this part depending on what signals you are actually using and what is power and ground. That is because this is only a 4 row part. You may be able to squeeze row AC between AD and AB between AA and get it fanned out with say a .2mm drill in a .45mm-.50mm pad or some such away from the balls. To fan out a .5mm BGA this way you are going to need .083mm (3.28 mills) trace and space which is still way small, so again start with your fab house to see what they can do.

If your using PADS you may want to hit the PADS newsgroup where there are lots of people with experience in this kind of stuff hanging out. PADS is NNTP server - listserver.pads.com with the newsgroup "Talk"

Hawker

On 3/19/2007 3:35 AM, The digits of Joe G (Home)'s hands composed the following:

Reply to
Hawker

is that the LPC3180 you are using? wonderful chip

Reply to
bungalow_steve

That is indeed sex-on-a-stick.

Dave.

Reply to
David L. Jones

My suggestion will be a bit more practical tha others. Absolutely use no less than 6 layers. Being new to it, you will end up chewing up your ground/power planes and will have EMI issues if you try 4. Even an experienced layout guy would most likely use 6, I know I probably would unless I was using very few pins. The reason is simple: it ends up a better design. For you, it will be a less frustrating experience to learn with 6 layers and you will definitely have a better design. Don't think I am calling you incompetent, most times parts like these just aren't good candidates for 4 layer boards.

Use a stack up as in Figure 6 here...

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Thats my advice.

Brian

---------------------------- Rising Technologies, inc.

Reply to
Brian

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Got a reason, other than some hand waiving? I don't see any reason for more than five. Four might be simple, depending on the power ball layout.

--
  Keith
Reply to
krw

here...

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First, let me ask for some help....

SED participants, how do I answer a guy that just said this was realistic to put on a five layer PCB?????

Do you ever purchase PCB's AT ALL!?!?!

Reply to
Brian

the

here...

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Why? I've done three (years ago). Why not five?

Nope. Buyers do that.

You still haven't answered the question.

--
  Keith
Reply to
krw

On 3/20/2007 1:27 AM, The digits of Brian's hands composed the following:

All perspective I guess. If you asked me how to break out this board, and suggested 5 layers I would assume you meant 5 ROUTING LAYERS or in other words an 8 layer board. 5 routing, 1 ground, 1 VCC, 1 Vcore. I find that some people refer to layers as only routing layers and ignore plane layers in the count. I never understood that logic but I often see it. Perhaps this is what they were saying.

Hawker

Reply to
Hawker

the

here...

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BTW, five (2S3P) and seven (4S3P) were quite commonly used in mainframes in the '70s. The ECL used needed three power planes.

--
  Keith
Reply to
krw

His latest reply kinda blows that theory. Nice of you to give him the benefit of the doubt though.

Reply to
Brian

but the

here...

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There it is. Kind of hard to relate to a guy going on experience from the 70's electronics world. But as an exercise, go quote us some 5 layer boards today.

One main reason I would go with 6 layers is that he said he has a

60Mhz clock. Did you miss that?
Reply to
Brian

but the

here...

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Dimbulb, is that you?

You need all six layers to go that slow? You still haven't answered the question. Four layers should be enough given the specification.

--
  Keith
Reply to
krw

220MHz but the

use

Even

probably

ends

experience

design.

these

here...

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I have answered the question, you just do not have the ability to understand the details behind it. Do not assume your lack of knowledge belongs to anyone else.

On a 4 layer board, please tell us how you route faster clock signals between planes for minimum EMI. How long can they be/ how many vias can you put in them? What percentage of the planes is acceptable to be chewed up by vias and traces? Will you be able to isolate the I/O properly? Can you isolate AGND without routing across it? Or are you one of those slop dudes that skips EMI testing on your uC/uP products (oh, I bet I am correct here)?

Oh, I am sure you went all through that before recommending your "five" layer board. Did you get us some quotes on that? Did you Google for "5 layer PCB"? How many results did you get? Great suggestion.

Advice based on a complete lack of knowledge is not worth very much, but at least no one paid you for it.

Reply to
Brian

220MHz but the

Absolutely use

up

Even

probably

ends

experience

design.

these

here...

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ball

No, you've only waived your hands. Sorry, I asked a question that specifically asked for an answer other than hand waiving.

The same way you do it on a hundred. the number of signal planes doesn't matter much (until you run out of routing space).

Information not supplied. Don't start pretending now.

All information not supplied. There was only a BGA footprint and some mention of 60MHz, neither of which is very hard on four layers. The inner balls may be a bit tough routing out but most often that isn't needed. Other than the inner ring, only one trace per channel is needed. Hardly a big need for more layers there.

Nope. Standard product. Pick a number (zero to eight, at the time).

You still haven't answered the question, not that I'm surprised anymore. You can't.

You are really Dimbulb, aren't you?

--
   Keith
Reply to
krw

,
220MHz but the

Absolutely use

chewing up

  1. Even

probably

it ends

experience

design.

like these

here...

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reason

ball

Do you even have a clue how stupid you look right now? Where does one start? First, you are telling me about "standard 5 layer boards" from THIRTY FIVE YEARS AGO! Irrelevant. Buying a 5 layer board now will cost you MORE than a 6. MORE than an 8. Its just stupid and ignorant. Again, show me a link on Google to a service offering standard 5 layer boards. Just one. I noticed you haven't done that yet as I suggested.

And because you are too stupid to understand the answer, you think you haven't gotten it? I am sure you have ZERO knowledge of clock signal rise times vs trace length vs EMI, but to any educated board designer, it is quite obviously covered by the mention of 60MHz clocks. I am also sure the benefits of seperating I/O from these signals is also not understood by you at all. Same with using gnd planes and signal planes as shields, alternate direction routing on adjacent planes, etc., etc., etc. I guess what should be obvious to most engineers is just beyond your grasp.

Out of 100 designs using the horsepower of a 220Mhz chip, how many are going to be so simplistic that you will not run across ANY of these issues? You think that it is a one-chip design? No analog? Only one voltage/power supply? No need to use the clock elsewhere on the board? No I/O or anything but supplies used from the inner rings? No requirement at all regarding EMI? I don't know how to say this any clearer, but you are a moron. Really, I am not kidding. Thank God above you haven't designed a board since 1970, they'd all be transmitting like beacons! (OK, I am giving you too much credit. They wouldn't likely operate at all)

The OP didn't ask "How can I do this like crap"? But thats how you answered. I think you have CLEARLY demonstrated the talent and knowledge of someone who would lay this out on a 4 layer board. Congratulations on being the negative example. What a fool. Probably maintains a DOS machine to use his CAD program.

Reply to
Brian

,
220MHz but the

Absolutely use

chewing up

  1. Even

probably

it ends

experience

design.

like these

here...

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reason

ball

This needed its own reply from you. I asked: On a 4 layer board, please tell us how you route faster clock signals between planes for minimum EMI.

You answered: The same way you do it on a hundred. the number of signal planes doesn't matter much (until you run out of routing space).

By your answer, that means you would not have ground and power planes on the 2 inner layers. So please explain the 4-layer build-up you would use.

Reply to
Brian

Could be a one-chip daughter board using a few dozen I/O pins for all we know.

Not uncommon.

Could be, and not all power supplies need a plane anyway.

Could very well be, plenty of outer pins there to be used. The OP would need to have a lot of I/O to use up all those pins. Depends on the chip and the requirements, neither of which we know.

Could be, you never know. Some stuff I design (e.g. stuff that sits

2km down on the ocean floor) does not need to meet any EMI standards, nor have any other strict EMI requirements apart from those internal to the design itself.

Dave.

Reply to
David L. Jones

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