Does anyone know where to fine documentation on the newer LT op-amp models available at the LTC web site (ie LT6202, LT1630)? There is an application note by Jung from about 1990 that discusses their older models but I can't find any documentation at all about the newer ones. What is modeled? How good is the representation of noise? In particular, does the current noise vary realisitically with common mode voltage? Thanks, John
John,
The newer LT opamp models use an internally developed model that allows current and voltage noise and corner frequencies to be modeled. These are generic SPICE models, not LTspice specific. But noise verses common mode voltage isn't modeled.
I'll separately e-mail you contact information for the guy who is making those models and the app engineer that should help you with the noise verses common node voltage.
--Mike
"Mike Engelhardt" a écrit dans le message de news:a2n%c.17160$ snipped-for-privacy@newssvr29.news.prodigy.com...
Mike, Any info, pointer on this, and how/why this happens ?
I've seen you make mention of this in a recent thread about shot noise. Very little info (read no info) on the subject exists in datasheets and I have to use a LT1128 in a very critical wrt to noise application.
-- Thanks, Fred.
Fred,
The noise can be dependent on common mode input voltage, particularly in something like a rail-to-rail input JFET opamps. It's not an issue in a bipolar design like the LT1128.
If you want, e-mail me at the address on LTspice's Help=>About box(I don't put the address anywhere else for spam reasons) and I'll give you the contact information for the apps engineer that can help you with noise on any LT opamp.
--Mike
The lack of a model you mean?
If so, probably because it doesn't change much to bother about. Offhand, about the only real mechanism that might change the noise is bias base/collector current noise. If the bias current changes with common mode voltage it will effect the noise a bit. I don't see this happening much though, certainly not for bipolar. Bias currents are usually pretty much independent of the CM voltage, they are set by a current source. For jfets bias current might vary quite a bit more, but then gate noise is often not significant for many sources.
There is an effect that can potentially reduce 1/f noise when Vce < 0, but this aint gonna happen in an opamp unless its designed to do this, or your at the rails.
I would just ignore noise with CM voltage if it were me. Just make sure you have a set of models that have a reasonable estimate of max and min noise over process variations at a spot CM voltage. These will be way more than that due to CM voltage variations.
Kevin Aylward snipped-for-privacy@anasoft.co.uk
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