Logic Question

Input stage has 3 states: 0, 1/2 and 1. Got it, you idiot?

m II wrote:

Crazy idea.. NPN transistor with emitter to resistor to control signal, collector with pullup resistor to +5; signal out at collector. Resistors of similar value.

"Jim Thompson" schreef in bericht news: snipped-for-privacy@4ax.com...

I think it's an analog problem rather then a logic one as logic does not dive below gate level :)

A quick look makes me think the problem is caused by the input signals that are to be inverted (3 stage) or not (2 stage). The old TTL chips provided "complementary output elements", the SN74265. Using this elements instead of normal inverters will provide 3 stage delays all the time.

petrus bitbyter

Input stage has 3 states: 0, 1/2 and 1. Got it, you idiot?

I mean something like what is done with a PAL

Oh! How Larkinesque :-)

Could you put some values (and device dimensions) on that sketch ?:-) ...Jim Thompson

A supposedly "symmetrical" structure with transition direction peculiarities. Because of the VDD1/VDD2 "spec" I have to tip-toe around cautiously ;-) ...Jim Thompson

Here is absolutely symmetrical XOR, it is also absolutely minimal :-)

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

I'm not getting across to you. Describe how that works. ...Jim Thompson

If the inputs are 01 or 10, both FETs are on, so the output = 1. If the inputs are 00 or 11, only one of FETs is on, output = 0. Minor technicalities omitted for clarity.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

Indeed ;-)

With the addition of ~10 additional components/gates I accomplish a

High: State 1

Float: State 2

Low: State 3

...Jim Thompson

I was thinking of the same thing, but it was the TTL 8-bit parity generator (don't remember the number), not the 7486. I think the parity generator/checker used 8 gates.

Apparently Jim doesn't have discreets on his ASIC or he would have liked this.

If it was driven by another like it, as in the parity tree. But couldn't it be driven high and low? (IANAEE)

Maybe he just did not read this part of the thread. Or I'm blacklisted. The beautiful symmetry should appeal to him.

No, hard driving one input high, the other low would overdrive conducting B-E junctions. And you need to pull the E's low hard to get the output at a logic low level. The base is then driven though the other pull-up.

Now I think of it, this piece or RTL logic with a twist even looks nicer (2x NPN):

|\ VCC A --| >-+------- E C -----+ | |/ | B | (R) \ /--(R)--+ | | X +------+--- OUT / \--(R)--+ | |\ | B | B --| >-+------- E C -----+ |/

A good bottle of dry white signed by Jim is OK to use this :-)

Arie

You missed the part where what I really need is two circuits, each with input A, but one with output A and the other with output Abar, delay to each output EQUAL.

What is your preference in dry white wine ?:-)

Unfortunately I'm on the wagon at the moment. Something untoward going on in my colon. Colonoscopy scheduled for Tuesday. Damned capitalist health care... 1 week delay (from Doctor's order) while I'm weaned from anti-inflammatory which could cause bleeding ;-) ...Jim Thompson

A week? It was over a year with the VA.