Eagle library editor

Hmm, so instead of bumping the rev level you add the ECO number? That's a new one to me, but works. Except I never have that much space on my boards to get that many characters into the white field. Max is two, maybe three.

Yup :-)

Usually my clients are quite good in that respect though because many are operating on heavily and federally regulated turf. Some of their vendors, different story. Occasionally we had to dump one because of it.

The rev letter is permanent, on the silk, so we don't need to Sharpie that in. A little sticker somewhere can tag the ECO. Plus, we have good records of the history of every board, by serial number.

I've seen people who rolled the rev letter on existing boards when they applied an ECO. So you might have a board that was born rev C and got ECOd to D, E, and then F, covered with blue wires. And right beside it was a board born as rev F, with no kluges. Often the way you do a kluge is different from the way you actually make a proper fix, so the two rev F boards actually are different circuits.

No thanks.

Besides, there are only 26 letters in the English alphabet!

Question to group: what's the highest rev letter you've ever seen?

I have a gigabuck-level customer that uses Agile, the Oracle does-everything database. We call it "Fragile". They call us and ask if we can furnish them a copy of their own documents.

We can't read the Terms&Conditions doc that they send with POs. It looks like a PDF scan of a copy of a fax. They can't find the original. They can't find firmware or FPGA designs, either. I'm designing to Requirements Documents that have multiple versions, different numbers of pages, all the same apparent rev and date. We'll get rev 2.0 from engineering and a different 2.0 from purchasing. We pretty much ignore them and design what we think will work.

I've sold about 4000 NMR temperature controllers because a British company, Ox**** In*********, lost the Z80 source code for theirs and couldn't fix bugs.

All of which is why we have a documentation system that is entirely unambiguous, and practically guarantees that you can edit a design 10 years after it's released.

John

Excuse my butting in but I think the above statement represents a somewhat limited perspective.

I've designed (as part of various teams) dozens of commercial IC's in the last 20 years, all full custom analog/RF/high-speed digital with well under 50% standard cell content. Die sizes ranged from ~1 mm to over 10mm /side with device counts sometimes exceeding 1e6.

Same here. The current one will break the 10mm side length, big time. Other than the RAM area nothing is standard cell in there.

Quite normal, although that's a lotta rev levels.

Short term fixes are usually done via deviation instead of ECO.

In heavily regulated industry segments you sometimes have to do it that way.

Don't remember, but I certainly do remember one rev G board.

That has more to do with management problems than Agile, maybe a botched implementation, maybe lack of training. Boils down to upper management, they have to set things in motion to fix that. We've used Agile at Endosonics and it worked great. I could find and access everything instantly. Production data, schematics, parts pricing, whatever I needed.

What I do remember is that I sat through at least 20h of training and that was well worth it.

Oops. I only know a finacial company by that name. And a headhuntuing biz that sometimes calls here.

That's what we had in both of the companies where I worked as an employee. My own system works that way as well. I recently needed a test set I built about 20 years ago. Blew one of the drivers on it, needed the schematic. Took five seconds to locate and pull.

You design your own diffusion shapes?

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Layout is dead. I didn't think Cadence supported others' formats at all.

Nothing special about EDIF, but it's it.

is

Lots of analog really is standard cell, in that the transistors are standard and in an array(ish); you can specify L/W and that's about it. No custom shapes.

Ten years ago there was more custom than there is today.

You think he designs the shapes? Maybe he'll answer (I'm off line so can't see what's gone on recently).

I'd

Not drowsy, just uninterested in working. ;-)

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Sometimes. Sometimes it means that management changed their mind. ;-)

One of the products at the PPoE had Rev-C as the first "working" board. It is still being shipped in one set of products. When I got there I did Rev-D to improve performance (so it would be acceptable in other markets). Rev-D worked well enough but didn't pass EMI, so there was a Rev-E to fix that and then Rev-F to fix an EMI problem with the daughterboard. There was also a rev to fix the hole sizes for a connector (to spec but too small). ...and I think one to eliminate a few plated-through holes (that shouldn't have been).

We had another that was up to 'M', I think, mostly because RF was getting into the audio and they were falling out in manufacturing. Much of that was tuning the "FM". ;-)

Probably.

is

At the PPoE, the schematic matched the raw board. The schematic wasn't ECOed unless the raw board was. The board had a rev silk screened in and a separate rev for the BOM (written in ink). Other design variations were done in BOMs, with (sometimes) notes made on the schematic. If multiple products were intended from the beginning, the part properties were used to denote the variations. BOMs were then generated offline (Excel) based on the parts properties.

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We started doing that for known engineering work (engineering used numbers for rev levels, then went to 'A' for the first production). The problem is that the first board was usually intended for production so that scheme didn't always work. Everything, outside of X-Acto boards, went through the ECO process. It needed an ECO before purchasing would touch it.

Your process is really the same as what Joerg is saying (and I'm familiar with). Instead of a letter representing the ECO you include the entire ECO number.

We had the board part number and rev "1234567-F" silkscreened onto the board, and like Joerg, behind that was a white markable area where the inspection tech would mark the BOM ECO letter (for example, the first ECO for the board would be an 'A'), so the entire number would be "1234567-FA". The next BOM, or yellow wire, number would be "1234567-FB" (with the 'B' in sharpie). If the raw board is ECO'd, the part number would be "1234567-GC" (I think).

No one is suggesting that. There is no control there at all.

AA, AB, AC,... How many now? ;-)

Raw board? 'M', I think (above). The RF problem was a bitch. For a BOM rev, I've seen two digits.

At they PPoE, they use pre-Oracle Agile. The CPoE uses the Oracle product. I can't find anything in it.

If you have no control, no program will give you control. Don't blame the tools on a poor process.

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That's what I thought as well. However, ...

So it's just another netlist format ...

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No arrays in mine, other than for mundane housekeeping stuff with is mostly digital.

But I am involved in an IC design right now and it's full custom except for the RAM :-)

He runs some ancient newsreader and blocks people who respond to people he doesn't like, so ...

Of course he won't design a transistor in the shape of a pretzel but I am sure he will use individual widths and lengths, have multiple gates here and there, a channel tap-off over yonder, and so on. In other words no array of standard cells.

Not yet :-)

But we do design our own geometries and do some unorthodox stuff with channel tap-offs and stuff. On one of them we had an extra deep etching process step in there that was non-standard for the process. I did have situations where we were turned down by serious players. You could almost see the neck hair come up as I went into the presentation about what we wanted to do :-)

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So they insisted on rev levels beig the same for board and assy? That doesn't make sense to me, it can lead to having to throw away good bare boards.

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I am used to X1, X2 and so on. Usually my designs are also first proto to production. Soif it all pans out well that first board is called X1 until the day the ECO is all signed off, then goes to A without any changes.

What does "deviation" mean? Is that an informal hack, or something documented that's different from an ECO?

We avoid getting tangled up with regulators.

John

It's generally a documented "deviation" from the normal process. There are many reasons for a deviation, like a part being out of spec (expected to be corrected with the next order). The deviation can be set to expire on any number of triggers, or not. Yes, it's a documented process but not intended to be permanent, like an ECO. In one case, purchasing neglected to order a transformer and ran low. We found a substitute but its inductance was far lower, resulting in less gain in the output stage. To help mitigate the problem I changed resistors in the output stage to drive it harder; not a perfect solution but it beat leaving money on the table. The deviation was written such that the alternate P/N could be used but the resistors had to be changed also. When the next batch of transformers came in, the deviation expired.

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Except the silkscreen still says X1? How does that work?

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No, did I say that? The board and schematic have the same Rev number. There can be several active P/Ns using the board and several ECOs of each using the same board and schematic. Such ECOs are documented by the BOM (which calls out the raw board, which in turn calls out the schematic). If there are "yellow wires" on the board, there will also be rework instructions in the ECO.