What is the cause of a "can not see clock" problem in logic analyser?


My LA is agilent 16702. When I use the 400MHz internal clock to sample
the clock pin and the data pin with probes, I can see them nicely on the LA,
and positive edge of the clock is right in the middle of the data. When I
change
to sampling data with my external clock pin, LA told me the clock is too
weak
and can not see a clock in the top-right banner. Of course, I don't see any
data.
What is the cause of that? How can I correct this?
Reply to
Acceed See
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LA,
any
Any quick fix for those "It worked in simulation, but not in FPGA" nightmares? My design is 200K ASIC gates burned in an FPGA, it's so tiring to debug that.
Reply to
Acceed See
What is the clock source? Is id overloaded or short on settling time?
Jerry
--
Engineering is the art of making what you want from things you can get.
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Reply to
Jerry Avins
I can think of a couple of reasons...
First, the "clock" signal on a 16500/16700 logic analyzer needs to be on specific pins - there is one pin per pod that is the clock pin for that pod. Also, the naming is not all that easy to determine - the name of the clock depends on which pod you are using (i.e. the "J" clock is the clock pin on pod D1). The mapping of clocks to pins is determined by which pods you have in what slots of the logic analyzer, so changes from LA to LA; go through the setup menus to make sure you have the right clock.
Second, the LA can deal with digital signals of different voltages; this allows it to monitor signals from different I/O standards. Each pin (or pod, I can't remember) must have the proper signal threshold programmed. This should be set to the proper value for the I/O standard you are using. The defaults may not necessarily be correct for the I/O standard you are using. For example, if you are using SSTL2, then the threshold MUST be set to 1.25V. If it is set to a different value, the LA will not "see" the transitions from the "0" to "1" on the clock.
Avrum
LA,
any
Reply to
Avrum

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