What is the cause of a "can not see clock" problem in logic analyser?

LA,
any


Any quick fix for those "It worked in simulation, but not in FPGA"
nightmares?
My design is 200K ASIC gates burned in an FPGA, it's so tiring to debug
that.

What is the clock source? Is id overloaded or short on settling time?

Jerry

I can think of a couple of reasons...

First, the "clock" signal on a 16500/16700 logic analyzer needs to be on
specific pins - there is one pin per pod that is the clock pin for that pod.
Also, the naming is not all that easy to determine - the name of the clock
depends on which pod you are using (i.e. the "J" clock is the clock pin on
pod D1). The mapping of clocks to pins is determined by which pods you have
in what slots of the logic analyzer, so changes from LA to LA; go through
the setup menus to make sure you have the right clock.

Second, the LA can deal with digital signals of different voltages; this
allows it to monitor signals from different I/O standards. Each pin (or pod,
I can't remember) must have the proper signal threshold programmed. This
should be set to the proper value for the I/O standard you are using. The
defaults may not necessarily be correct for the I/O standard you are using.
For example, if you are using SSTL2, then the threshold MUST be set to
1.25V. If it is set to a different value, the LA will not "see" the
transitions from the "0" to "1" on the clock.

Avrum



LA,
any