Has anyone managed to get the xilinx BSCAN primitives (for interfacing with the USERx jtag registers/comands) working robustly? I've found a depressing lack of information as to what the actual pins do -- aside from a (now unavailable?) techXclusive article, "Reconfiguring Block RAMs - Part 1" (by Kris Chaplin, available via google cache) I can't find much more info.
What's the best way to interface with this part? In particular, how do you deal with the obvious synchronization/metastability issues when crossing clock domains, esp. if you're hoping for a device that's still small (i.e. no hardware async fifos or anything).
Thanks for any advice you can provide, ...Eric