Hello, Im a student doing some under-graduate work for my final year project. It involves moving Bscan functionality onto the board so we kind of augment the DUT with some hardware for test purposes (remote testing is a big incentive to move towards this). Hence we generate JTAG on the board itself and talk to the test manager(PC S/W) using some faster protocol like LAN for instance.
Curently the test patterns for testing a board (both with bscan and non-bscan components) are stored on the PC memory. To that end, all sorts of diagnostic features for determing and localizing the fault down to the device pin are implemented in the Test Manager.
Now have moved a couple of functions from the Test Manager to an on- board module. This module is a mixed H/W - S/W module. But the solution is rather rudimentary and theres no fault tracing implemented on the module yet. Plus we still route the test patterns from the Test manager. We want that to be stored somehow on the board itself.
Now thats what im supposed to think about. So the first thing that comes to my mind is how would one go about storing the various patterns corresponding the various test choices the end user can make. The H/W module can generate the JTAG signals for the UUT (unit under test). And it takes with the S/W module which 'steers' the H/W module and is the brain of the board as far as DFT is concerned.
Now since this is my first ever real life work, im a bit confused about how to approach this problem. I have started reading some papers on the subject of fault dictionary compaction and means of testing clusters (group of Non-bscan components) using bscan components present on the board. Most of them are by P. Hansen from teradyne. I think the first problem we'd face is storage of test data. Hence the choice above.
By the way,what is really meant by 'fault dictionaries' since we would be only storing the expect values not a sort of a LUT which points to faults and prints human readable messages. Could anyone please elaborate?
I would kindly request people on the group to analyze my approach to this and guide me a little as where I should be looking towards. Since this work encompasses DFT techniques and a lot of thinking with regards to the embedded solution as well, i suppose people on this forum could certainly have things to say to help me move in the right direction
Any suggestions would be highly appreciated Regards and thanks for reading through this rather long post, AB