I looked up my ucf file, board schematics and pin definitions. If i'm correct, the error is generated by the fact that:
IO pins on bank 3 are of type SSTL2_I. Because pin 'SDR_CLK_FB' is a input of type SSTL2_I, which is not a standard type like LVTTL, the bank needs to use a Vref pin to be able to recognize the logic level (1 or 0) of input 'SDR_CLK_FB'. This is then becoming a problem beacause the Vref pin is already used as output signal 'BA0'. Therefor the compiler tells me that this input 'SDR_CLK_FB' on bank 3 cannot be used, in other words "locked to the I/O bank 3".
As many of you know, BA0 and BA1 are 'Bank Select' signals used to select 1 of 4 memorybanks in the DDR SDRAM, and to access the 'Mode register (B1=0 and BA0=0) or the 'Extended Mode Register ((B1=0 and BA0=1)'. The 'SDR_CLK_FB' (SDRAM Clock Feedback) signal is used for clock deskew using Virtex-4 DCMs.
What can i do to solve this problem?
In advance thanks, Maurice