Vref IO problems with DDR SDRAM memory controller on a Virtex 4 LX25, ML401 board

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Hi all,

I'm trying to write a memory controller to make the use of DDR SDRAM
possible. It's not going to be a high speed memory controller, but a
basic one. The problem i encounter is with implementing the design
(place and route stage). The error given says:

****************************************************************************************************************************
Place:897 - The following IOBs have been locked (LOC constraint) to
the I/O bank 3.
They require a voltage reference supply from the VREF pin(s) within
the same I/O bank to be available.
The following VREF pins are currently locked and can't be used to
supply the necessary reference
IO Standard: Name = SSTL2_I, VREF = 1.25, VCCO = NR, TERM = NONE
List of locked IOB's:
    SDR_CLK_FB
List of occupied VREF Sites:
VREF site IOB_X1Y136 is occupied by comp BA<0>
****************************************************************************************************************************

I looked up my ucf file, board schematics and pin definitions. If i'm
correct, the error is generated by the fact that:

IO pins on bank 3 are of type SSTL2_I. Because pin 'SDR_CLK_FB' is a
input of type SSTL2_I, which is not a standard type like LVTTL, the
bank needs to use a Vref pin to be able to recognize the logic level
(1 or 0) of input 'SDR_CLK_FB'. This is then becoming a problem
beacause the Vref pin is already used as output signal 'BA0'. Therefor
the compiler tells me that this input 'SDR_CLK_FB' on bank 3 cannot be
used, in other words "locked to the I/O bank 3".

As many of you know, BA0 and BA1 are 'Bank Select' signals used to
select 1 of 4 memorybanks in the DDR SDRAM, and to access the 'Mode
register (B1=0 and BA0=0) or the 'Extended Mode Register ((B1=0 and
BA0=1)'. The 'SDR_CLK_FB' (SDRAM Clock Feedback) signal is used for
clock deskew using Virtex-4 DCMs.

What can i do to solve this problem?

In advance thanks,
   Maurice

Re: Vref IO problems with DDR SDRAM memory controller on a Virtex 4 LX25, ML401 board

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If you can rewire the PCB, then avoid the conflicting pinout.

If you can't, then ... note, the only pin LISTED as requiring SSTL2-I
input type in this bank is your own clock feedback pin. So verify that
it is only connected to a spare clock output (e.g. by reading the board
schematics) and, if so, set it to another input standard, e.g. LVTTL or
LVCMOS.

- Brian


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