Summary: Should high-speed shift registers (purely DFFs) flow left->right, top->bottom, or does it matter?
Doing a Virtex4 (LX100). I wound up with high-speed inputs (clocks and serial data) on the IOBs that run vertically down the center of the die. OK for clocks, since the DCMs and BUFGs are also in that center column.
Regarding data: I deserialize the inputs, and pass parallel data to some large datapath blocks that start on the left edge of the die. I constrain all my deserializer logic to use sites near the center column to minimize clock skew. (Sorry, I can't use the on-chip deserializers; they max out at 10 bits, and I need 12.)
Kind of annoying to take my inputs from the center over to the left, and then start flowing left-to-right, but that's just how the layout wound up...
Anyway, older Xilinx docs say you should flow left->right, and numerical operations should have their MSB flowing downward (?) to make best use of carry chains. Is that still the case?
Back to my deserializers: I'm using 20 of them, so that's 40 6-bit shift registers (6 bits on rising edge, 6 bits on falling edge), which I plan to do manual placement on. I don't want to use the SRL16's (yet; long story...), but just DFFs.
I thought left->right flow was perfect for shift registers, but ISE seems to place all the DFFs for a downward flow. Actually, since my inputs are all down the center column (20 serial data streams) and need to go left, horizontal alignment flowing right-to-left makes for best placement. Not sure about routing though...
Any suggestions? The data is coming in close to 1Gbps, so the shift regs run close to 500 MHz...
Thanks again for all the help; I'll appreciate your input as I work another weekend...