I just got my new ISE and went straight to synthesizing some of my old designs. Basically, I'm planning on publishing soon, and figured the Virtex-4 would bolster my numbers even further. However, that wasn't the case.
****************************************************************** ****************************************************************** Virtex-4 Timing ****************************************************************** ****************************************************************** Timing constraint: Default period analysis for Clock 'clk' Delay: 3.445ns (Levels of Logic = 0) Source: ksb10_sb3_Mrom__n00001_inst_ramb_0 (RAM) Destination: rcx10_t5_25 (FF) Source Clock: clk rising Destination Clock: clk risingData Path: ksb10_sb3_Mrom__n00001_inst_ramb_0 to rcx10_t5_25 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ RAMB16:CLKA->DOA1 1 1.830 0.470 ksb10_sb3_Mrom__n00001_inst_ramb_0 (t1_9) FDR:R 1.145 rcx10_t5_25 ---------------------------------------- Total 3.445ns (2.975ns logic, 0.470ns route) (86.4% logic, 13.6% route)
****************************************************************** ****************************************************************** Virtex-2 Pro Timing ****************************************************************** ****************************************************************** Timing constraint: Default period analysis for Clock 'clk' Delay: 2.297ns (Levels of Logic = 0) Source: ksb10_sb3_Mrom__n00001_inst_ramb_0 (RAM) Destination: rcx10_t5_25 (FF) Source Clock: clk rising Destination Clock: clk risingData Path: ksb10_sb3_Mrom__n00001_inst_ramb_0 to rcx10_t5_25 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ RAMB16_S36:CLK->DO1 1 1.401 0.360 ksb10_sb3_Mrom__n00001_inst_ramb_0 (t1_9) FDR:R 0.536 rcx10_t5_25 ---------------------------------------- Total 2.297ns (1.937ns logic, 0.360ns route) (84.3% logic, 15.7% route)
************************************************************** **************************************************************...So, you'll notice the critical path is identical in both. However, it seems flat-out that both the logic and the routing is slower in the Virtex-4. I'm a little disappointed, as I've heard claims of 500 MHz all around, and I'm not seeing it. I would've been happy just with some faster logic, but slower I don't understand.
By the way, this holds across all types of Virtex-4 devices. Among other architectures of this particular application (encryption) Virtex-4 is slower. However, I did notice that for my FIR filters and FFTs I have a huge increase in speed. Am I just out of luck on this application, or am I missing something?