Virtex-4 Slower than V2Pro?

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I just got my new ISE and went straight to synthesizing some of my old
designs. Basically, I'm planning on publishing soon, and figured the
Virtex-4 would bolster my numbers even further. However, that wasn't
the case.

******************************************************************
******************************************************************
Virtex-4 Timing
******************************************************************
******************************************************************
Timing constraint: Default period analysis for Clock 'clk'
Delay:               3.445ns (Levels of Logic = 0)
  Source:            ksb10_sb3_Mrom__n00001_inst_ramb_0 (RAM)
  Destination:       rcx10_t5_25 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: ksb10_sb3_Mrom__n00001_inst_ramb_0 to rcx10_t5_25
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16:CLKA->DOA1     1   1.830   0.470
ksb10_sb3_Mrom__n00001_inst_ramb_0 (t1_9<1>)
     FDR:R                     1.145          rcx10_t5_25
    ----------------------------------------
    Total                      3.445ns (2.975ns logic, 0.470ns route)
                                       (86.4% logic, 13.6% route)

******************************************************************
******************************************************************
Virtex-2 Pro Timing
******************************************************************
******************************************************************
Timing constraint: Default period analysis for Clock 'clk'
Delay:               2.297ns (Levels of Logic = 0)
  Source:            ksb10_sb3_Mrom__n00001_inst_ramb_0 (RAM)
  Destination:       rcx10_t5_25 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: ksb10_sb3_Mrom__n00001_inst_ramb_0 to rcx10_t5_25
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16_S36:CLK->DO1    1   1.401   0.360
ksb10_sb3_Mrom__n00001_inst_ramb_0 (t1_9<1>)
     FDR:R                     0.536          rcx10_t5_25
    ----------------------------------------
    Total                      2.297ns (1.937ns logic, 0.360ns route)
                                       (84.3% logic, 15.7% route)


**************************************************************
**************************************************************

...So, you'll notice the critical path is identical in both. However,
it seems flat-out that both the logic and the routing is slower in the
Virtex-4. I'm a little disappointed, as I've heard claims of 500 MHz
all around, and I'm not seeing it. I would've been happy just with
some faster logic, but slower I don't understand.

By the way, this holds across all types of Virtex-4 devices. Among
other architectures of this particular application (encryption)
Virtex-4 is slower. However, I did notice that for my FIR filters and
FFTs I have a huge increase in speed. Am I just out of luck on this
application, or am I missing something?

Re: Virtex-4 Slower than V2Pro?

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I did some test builds on my InfiniBand cores and I found that the Virtex
4 numbers were better than the V2P number but not by nearly as much as the
-speed numbers would indicate. With the V2P20-6 my cores can run upto
133MHz, with the -11 speed of the V4 I was getting 154MHz, the -10 speed
was running around 5% faster than the V2P-6. The speed tables that are in
the current tools release must be pretty preliminary so we should all take
whatever number we are getting with a grain of salt. Never the less it
would be nice if Xilinx would try to keep the -speed number reasonably
consistant from family to family.


Re: Virtex-4 Slower than V2Pro?
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[snip]

Doesn't the Virtex-4 have integrated registers avaliable in the output path?
A direct recompile might not provide the numbers you need (it's always nice
when all the timing numbers improve in a generation without giving the
design any thought) but if the delay is significantly less going from the
embedded registers to the logic, you might be able to get better timing.  Of
course the pipelining changes might be annoying.

Keep in mind that the timing for control signals - the reset in your case -
can be significantly different between families and even between logic and
I/O within a device.  Checking the timing numbers for the control paths with
the speedprint utility might give you insight into bettering your times.



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