VHDL Bus Macro for V2Pro

Dear

i am exercising a basic flow of partial configuration from xapp290.pdf In the example (verilog), bm_4b_v2 component is used.

Problem is that I do not know VHDL component of Bus Macro for Virtex II pro. It will be nice if someone tell me name of component of Bus Macro and how to instantiate it .

Thankyou in advance