Hi *,
I'm trying to do a module-based partial reconfiguration flow on a Virtex2Pro (xc2vp7) according to xapp290 (I'm using ISE6.1i w/SP3).
Par always fails in the final assembly phase with this error message:
"FATAL_ERROR:Guide:basgitaskphyspr.c:255:1.28.20.2:137 - Guide encountered a Logic0 or Logic1 signal GLOBAL_LOGIC1_156 that does not have a driver or load within the module boundary. This problem may be caused by having a constant driving the input from outside the module boundary or because a driver or load comp did not meet the par-guiding criteria."
When I open the .ncd fo the placed and routed module in FPGAEditor and look at GLOBAL_LOGIC1_156, it's directly connected to a VCC site that is definitely WITHIN the module boundary, as is the entire signal and all components it is connected to.
Has anyone else encountered this? I could find nothing about this on Xilinx's website, and the error message itself is not particularly helpful. If a "driver or load comp did not meet the par-guiding criteria", how can I find out WHICH component is responsible, and what can I do about it?
cu, Sean