Modify Memory after P&R in Xilinx Virtex2

Hi all,

I am building a design for a Virtex2 3000, including a ROM. The problem is I would like to be able to modify the ROM content, after placement and routing, without doing the placement and routing everytime. I know about FPGA editor, that allow to modify memories after P&R, but only by hand, word after word. Does somebody knows about a way to modify it from a .coe, .cfg, or .mif file?

Thanks in advance,

Yann