Synplify_pro

I 've generated 18x18 block based multipliers using Synplify_pro tool. Now I want to generate logic based multipliers( which dont use blocks ). I 've no knowledge on the contsraint files used to generate multipliers using synplify_pro. Can any one let me know on how I can generate logic based multipliers.

The following is the .prj file used to generate 10x33 block based multiplier.

#-- Synplicity, Inc. #-- Version 7.3.4 #-- Project file ./Mult10x33/Mult_mult10x33.prj #-- Written on Wed Feb 25 16:47:33 2004

#add_file options add_file -vhdl mult10x33.vhd

#implementation: "rev_1" impl -add rev_1

#device options set_option -technology VIRTEX2 set_option -part XC2V40 set_option -package CS144 set_option -speed_grade -6

#compilation/mapping options set_option -default_enum_encoding default set_option -symbolic_fsm_compiler 1 set_option -resource_sharing 1 set_option -use_fsm_explorer 0

#map options set_option -frequency 1.000 set_option -fanout_limit 10000 set_option -disable_io_insertion 1 set_option -pipe 0 set_option -update_models_cp 0 set_option -verification_mode 1 set_option -fixgatedclocks 0 set_option -modular 0 set_option -retiming 0

#simulation options set_option -write_verilog 1 set_option -write_vhdl 1

#automatic place and route (vendor) options set_option -write_apr_constraint 1

#set result format/file last project -result_file "rev_1/mult10x33.edf"

#implementation attributes set_option -vlog_std v2001 impl -active "rev_1"

Use the syn_multstyle attribute. From the Synplify reference manual:

------------- VHDL Syntax and Example

attribute syn_multstyle of object : object_type is "block_mult | logic | lpm_mult" ; library ieee; use ieee.std_logic_1164.all;

-use ieee.std_logic_unsigned.all;

entity onereg is port ( r : out std_logic_vector(15 downto 0); en: in std_logic; a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); c : in std_logic_vector(15 downto 0) ); end onereg;

architecture beh of onereg is signal temp : std_logic_vector(15 downto 0);

attribute syn_multstyle : string; attribute syn_multstyle of temp : signal is "logic";

begin temp knowledge on the contsraint files used to generate multipliers using

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