Strange power up issue on Virtex4

Are you selecting the programming mode with a dip switch? If so are you sure they are wired correctly and not feeding one of i/o bank voltages or dcio lines or shorted to any other pins?

Also, in the past when I had bizarre behavior like this I usually ended up scouring through the options in "Generate Programming File". Sometimes options that seem to be totally unrelated can have major impacts.

Hi Anonymous,

the programming mode is selected with strap-resistors. I have checked these and I am sure these are fine. This is a board we have been using for more than 6 months now, we haven't seen any real issues on completing the configuration phase (doen pin goes high), except for now where it seems that right after configuration something strange happens when the FPGA starts up with our bitstream. I will follow your suggestion and try looking into the different bitgen options now and hope for the best :-)

best regards, Bart De Zwaef

Hi Aurelian,

my answers :

1. we start from the same bitfile where startup-clock is set to = CCLK. This is no problem because for JTAG configuration we use Impact or Chipscope and these tools replace the startupclock=CCLK in our bitfile automatically by startupclk=JTAGCLK. So apart from that different startup-option it really is the same configuration bitstream.
2. It is slave serial configuration : we use an external controller to program the devices.

Just to make clear : the FPGA-done pin goes high at end of config as it should. Everything *seems* to behave normally and we have worked with this board + fpga-config stream for several months now. No real issues with functionality. But now I measure my output-clock and I notice we don't have any headroom left on our timing budget due to a supposedly slow output driver.

I hope this clears up the situation.

Best regards, Bart

the startup behaviour for slave serial and jtag is a little different, the way the actual 'startup' sequence is sent, etc..

done=1 doesnt meant that FPGA is configured or started it is possible that done goes high by jtag config while

1) FPGA is completly empty, no config at all 2) FPGA is loaded is corrupted bitstream 3) FPGA is loaded but not started GHIGH=0

but none of those seem to apply in your case, still check out the bitgen options and what is maybe even better, if you have suitable clock then use a USER clock as startup clock!

of course sending a few more CCLKs after bitstream can also fix a problem sometimes it is safe to stream in plain .BIT file with extra leading bulls*** and shift in any ff's after the actual bitstream is completed (sure not to send sync again!)

Antti PS I did not know that ChipScope is now fixing the startup clock, a few revisions ago it did not do that

Antti,

I am not sure on the fixing of the startup clock by Chipscope. I just assumed Chipscope does this, but never mentions it. I have additional info on that and to me it makes this situation even stranger : When we config with Impact => Impact says it replaces CCLK by JTAGclk => "programming succesful", but GHIGH=0 When we config with Chipscope => chipscope does not replace CClk (?) =>

"programming succesful", and GHIGH=1.

Could this strange behaviour of the tools be related to our problem ?

Bart

well GHIGH is the signal that actually releases the IO enables!

but if it is not asserted properly then it usually looks like all IO are input only, you seem to have partially/wrong enabled IOs

any if there is some mess with GHIGH then it sounds like the right place to keep digging

Antti

Problem is fixed ! And yes, it was the (lack of) extra CCLK cycles that was causing the problem.

To be more precise : actually we provided about 200 CCLK-cycles of clock activity after done goes high, but the small CPLD in between our controller and our fpga masked this.

CPLD programming is changed, and fpga configures ok and starts up ok with a clean fast output clock.

Thanks to all for suggestions. best regards, Bart