Hallo, I have made a state machine. When I synthetize it, XST adds lots of BUFG to states.
My code:
type state_type is ( seq_daq_state_1, seq_daq_state_2, seq_daq_state_3, seq_daq_state_4, seq_daq_state_5, seq_daq_state_6, seq_daq_state_7, seq_daq_state_8, seq_daq_state_9, seq_daq_state_10, seq_daq_state_11, seq_daq_state_12, seq_daq_state_13, seq_daq_state_14, seq_daq_state_15, seq_daq_state_16, seq_daq_state_17 );
signal seq_daq_state, seq_daq_next_state : state_type;
Here the log:
---------------------------------------------+---------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
---------------------------------------------+---------------------------------------+-------+
USER_LOGIC_I__n0065(USER_LOGIC_I__n00651:O) | NONE(*)(USER_LOGIC_I_rx_data_received)| 1 |
USER_LOGIC_I__n0064(USER_LOGIC_I__n00641:O) | NONE(*)(USER_LOGIC_I_interrupt_0) | 1 |
OPB_Clk | BUFGP | 237 |
USER_LOGIC_I_Clk_Spi_I_prescaler_out:Q | BUFG | 7 |
USER_LOGIC_I_tx_state_FFd2:Q | NONE | 1 |
USER_LOGIC_I__n0062(USER_LOGIC_I__n00621:O) | NONE(*)(USER_LOGIC_I_interrupt_1) | 1 |
USER_LOGIC_I__n0221(USER_LOGIC_I__n0221183:O)| NONE(*)(USER_LOGIC_I_Adc_Mux_0) | 3 |
USER_LOGIC_I__n0060(USER_LOGIC_I__n00601:O) | NONE(*)(USER_LOGIC_I_Spi_Ss_0) | 1 |
USER_LOGIC_I__n0059(USER_LOGIC_I__n00591:O) | NONE(*)(USER_LOGIC_I_interrupt_2) | 1 |
USER_LOGIC_I__n0058(USER_LOGIC_I__n00581:O) | NONE(*)(USER_LOGIC_I_Spi_Ss_1) | 2 |
USER_LOGIC_I__n0057(USER_LOGIC_I__n00571:O) | NONE(*)(USER_LOGIC_I_interrupt_3) | 1 |
USER_LOGIC_I__n0056(USER_LOGIC_I__n00561:O) | NONE(*)(USER_LOGIC_I_interrupt_4) | 1 |
USER_LOGIC_I__n0055(USER_LOGIC_I__n00551:O) | NONE(*)(USER_LOGIC_I_interrupt_5) | 1 |
USER_LOGIC_I__n0054(USER_LOGIC_I__n00541:O) | NONE(*)(USER_LOGIC_I_interrupt_6) | 1 |
USER_LOGIC_I__n0053(USER_LOGIC_I__n00531:O) | NONE(*)(USER_LOGIC_I_interrupt_7) | 1 |
USER_LOGIC_I__n0052(USER_LOGIC_I__n00521:O) | NONE(*)(USER_LOGIC_I_tx_shift_enable) | 1 |
USER_LOGIC_I__n0051(USER_LOGIC_I__n00511:O) | NONE(*)(USER_LOGIC_I_rx_shift_enable) | 1 |
USER_LOGIC_I_seq_daq_state_FFd17:Q | BUFG | 16 |
USER_LOGIC_I_seq_daq_state_FFd15:Q | BUFG | 16 |
USER_LOGIC_I_seq_daq_state_FFd13:Q | BUFG | 16 |
USER_LOGIC_I_seq_daq_state_FFd11:Q | NONE | 16 |
USER_LOGIC_I_seq_daq_state_FFd9:Q | BUFG | 16 |
USER_LOGIC_I_seq_daq_state_FFd7:Q | BUFG | 16 |
USER_LOGIC_I_seq_daq_state_FFd5:Q | BUFG | 16 |
USER_LOGIC_I_seq_daq_state_FFd3:Q | NONE | 16 |
---------------------------------------------+---------------------------------------+-------+
(*) These 14 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
In this way my project is overmapped, because it uses 10 GCLK.
In what way could I resolve this trouble?
There is a way to substitute BUFG with IBUF, in example?