Hi,
Are you working on Dynamic Partial Reconfiguration (DPR)? Are you strugglin g to get your DPR design working? Are you frustrated with using ChipScope?
I am a PhD student from the University of New South Wales, Australia, and I am very interested in the Partially Reconfiguration, particularly the func tional verification of Partially Reconfigurable designs.
Similar to traditional static FPGA designs, DPR designs are also created by writing Verilog/VHDL code. However, the design source can not be simulated because HDL simulators do not support RTL simulation of partial reconfigur ation. Traditional HDL languages assume that the design hierarchy is define d at compile-time and can not be changed in the middle of a simulation run.
I am currently working on an open source library, ReSim, for simulation-bas ed functional verification of DPR designs. By compiling the library and you r design HDL source, you can perform cycle-accurate RTL simulation of your DPR design, including the partial reconfiguration process, in HDL simulator s such as ModelSim. The designer can view in the waveform window all the si gnal transitions during the reconfiguration process, such as the transfer o f the partial bitstreams and the subsequent swapping of reconfigurable modu les.
You can find my latest ReSim library on Google Code:
You are welcome to use it and I would be happy to hear from you any feedbac k of using the tool.
Thanks and Kind Regards,