Hi,
> I am using Virtex II Pro (XC2VP30, package ff896) board to read 8 bit
> parallel data from FPGA. The output from the chip is of level 1.2V and
> hence I am using SSTL2_II IO standard for the inputs from the chip to
> the FPGA. I had designed my board to use the Pins A20 to A27 of the
> High speed IO bank J37 for reading the inputs from the chip.
> I have shared the ucf files for the not working and working case in
> the links below.
>
> not working ucf:
formatting link
QtNTQ3Ny00YzUw...
> working ucf:
formatting link
Y3Yi00MDFj...
> In the working ucf file, the only change I have done is, I have not
> used A23 and instead A31 pin of J37(L8 pin of FPGA). I checked with
> the Virtex II Pro data sheet and don't see any problem using A23 pin
> of J37. In fact, even if I remove all other constraints and just use
> the A23 pin also, I get the same error: Below is the link to the .par
> file for this failed trial.
>
>
formatting link
.
> ERROR:Place:897 - The following IOBs have been locked (LOC constraint)
> to the I/O bank 3.
> =A0 =A0They require a voltage reference supply from the VREF pin(s) withi=
n
the same I/O bank to be available.
> =A0 =A0The following VREF pins are currently locked and can't be used to
> supply the necessary reference
> =A0 =A0IO Standard: Name =3D SSTL2_II, VREF =3D 1.25, VCCO =3D NR, TERM =
=3D NONE
=A0 =A0List of locked IOB's:
> =A0 =A0 =A0 =A0 DATA_OUT
> =A0 =A0List of occupied VREF Sites:
> =A0 =A0VREF site PAD289 is occupied by comp DATA_OUT
>
> Is there something fishy about this A23 pin of J37 bank of the board?
> If I use LVTTL IO standard, it works fine, but I can't read 1.2 volts
> in that standard. Why is the behavior of this particular pin
> dirrefent from all it's adjacent pins? Is there any other IO standard
> which can help reading 1.2 Volt as logic high? I have confirmed that
> it doesn't work for IO standard=3D SSTL2_I too.
> If there is any document to explain this strange behavior, please
> point me to that.
>
> Waiting for some helpful answers.
> Thanks and regards,
> Pratap
> I am using Virtex II Pro (XC2VP30, package ff896) board
You need to explicitly state which board that you are using as there are many boards, from many vendors. When you reference pins of a connector (A20 to A27 of J37) there is no context to allow the reader to understand how this relates to the device.
used A23 and instead A31 pin of J37(L8 pin of FPGA).
If only you had said what J37.A23 was connected to on the FPGA as well as the working J37.A31 pin... The L8 pin is in PAD183 (IO_L41N_2) in Bank 2.
List of occupied VREF Sites:
> VREF site PAD289 is occupied by comp DATA_OUT
PAD289 in a XC2VP30-FF896 is pin AE1 (IO_L39N_3/VREF_3) in Bank 3. The pin that you have assigned that connected J37.A23 to the FPGA must be in Bank 3 and this is in conflict with the IOSTANDARD banking rules.
SSTL (all flavors) is a single-ended referenced IO standard and it requires an external reference voltage of 1.25V to work. In the XC2VP30-FF896 Bank 3 these pins are U2, W1, AA1, AB2, AE1, AE3 and AH1 and the 1.25V reference voltage must be applied to all of these pins and they cannot be used for any other purpose. Your design is attempting to use one of these pins as an I/O and this is not allowed.
You cannot fix this problem by reassigning the DATA_OUT to another location without also modifying your board to provide the required
1.25V to the 7 VREF pins in Bank 3.
Ed McGettigan
-- Xilinx Inc.