I'm trying to get a Virtex4 PPC405 boot loader to run an ELF file stored in DRAM.
I have setup the PPC to read binaries from an RS232 and store them in the DRAM. I've also setup my PC to transfer an ELF file to the PPC. Now I want to execute the ELF from DRAM, but it isn't working. Using checksums, I've verified that the file is transferred correctly.
My DRAM starts at 0x00000000, I'm using the XMK function elf_process_create(0, 0) to try to launch the process. My linker script for the ELF code I'm trying to launch is attached below. This was generated by the Xilinx EDK, with the entry point changed to _start from _boot. Is there anything obvious I'm doing wrong? I'm pretty new to this stuff, and any advice would be appreciated.
Thanks in advance,
-Till Rosenband
/* Linker script: */ _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x1000; _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000;
/* Define Memories in the system */
MEMORY { DDR_SDRAM_32Mx16_C_MEM0_BASEADDR : ORIGIN = 0x00000000, LENGTH =
0x03FFFFFF }/* Specify the default entry point to the program */
/* ENTRY(_boot) STARTUP(boot.o) */
ENTRY(_start)
/* Define the sections, and where they are mapped in memory */
SECTIONS { .text : { *(.text) *(.text.*) *(.gnu.linkonce.t.*) } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.init : { KEEP (*(.init)) } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.fini : { KEEP (*(.fini)) } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.rodata : { __rodata_start = .; *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) __rodata_end = .; } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.sdata2 : { __sdata2_start = .; *(.sdata2) *(.gnu.linkonce.s2.*) __sdata2_end = .; } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.sbss2 : { __sbss2_start = .; *(.sbss2) *(.gnu.linkonce.sb2.*) __sbss2_end = .; } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.data : { __data_start = .; *(.data) *(.data.*) *(.gnu.linkonce.d.*) __data_end = .; } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.got : { *(.got) } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.got1 : { *(.got1) } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.got2 : { *(.got2) } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.ctors : { __CTOR_LIST__ = .; ___CTORS_LIST___ = .; KEEP (*crtbegin.o(.ctors)) KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) __CTOR_END__ = .; ___CTORS_END___ = .; } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.dtors : { __DTOR_LIST__ = .; ___DTORS_LIST___ = .; KEEP (*crtbegin.o(.dtors)) KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) __DTOR_END__ = .; ___DTORS_END___ = .; } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.fixup : { __fixup_start = .; *(.fixup) __fixup_end = .; } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.eh_frame : { *(.eh_frame) } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.jcr : { *(.jcr) } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.gcc_except_table : { *(.gcc_except_table) } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.sdata : { __sdata_start = .; *(.sdata) *(.gnu.linkonce.s.*) __sdata_end = .; } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.sbss : { __sbss_start = .; *(.sbss) *(.gnu.linkonce.sb.*) __sbss_end = .; } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.tdata : { __tdata_start = .; *(.tdata) *(.gnu.linkonce.td.*) __tdata_end = .; } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.tbss : { __tbss_start = .; *(.tbss) *(.gnu.linkonce.tb.*) __tbss_end = .; } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
.bss : { __bss_start = .; *(.bss) *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); __bss_end = .; } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
/* Generate Stack and Heap Sections */
bss_stack : { . += _STACK_SIZE; . = ALIGN(16); __stack = .; } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
bss_heap : { . = ALIGN(16); _heap_start = .; . += _HEAP_SIZE; . = ALIGN(16); _heap_end = .; } > DDR_SDRAM_32Mx16_C_MEM0_BASEADDR
}