Can I do this all in a FPGA?
I would like to sync to an incoming pulse (its actually going to be a register write) that I will receive at approx 100hz, and generate a
8Khz output clock.This will be a recovered sync from a master device, but the devices are SW based so there will be a fair amount of jitter (~+/- 500us) .. but this jitter is expected to be bounded and stable (not slipping in time) over a long period.
Is it possible to use a local 50Mhz oscillator and create and up/down counter based on the 100hz signal, then slightly adjust the 8Khz clock rate based on this?
I=E2=80=99m a newbie so please bare with me =EF=81=8A.
Is there something out their like this? I did some searches, but seems most PLL type applications are not syncing to such a slow input (100hz). Also I am only concerened with long term frequency lock (well average) from the master providing the 100hz to the slave generating the 8Khz (the 100hz is based on the master 8K on the other side of the network, unfortunitly I cannot increase the 100Hz pulse rate)
I would like to try to keep this all digital if possible since I do not have a local PLL on board to work with.. I do have a Altera Cyclone II FPGA that I will be targeting for this application.
Thanks much!
-Bill