Newbie with questions on AT91RM9200

The memory width and the instruction width are separate. The bus interface is smart enough to use two 16 bit cycles for a single 32 bit instruction fetch. Besides, the processor always wakes up in 32 bit mode.

The narrow memory slows down the instruction feed to the processor, so baout half of the nominal speed can be expected.

You have also to protect the RAM control lines against glitches at power up and power down, to prevent corruption of the stored contents.

It depends entirely on what you write into the chip select registers at startup. Read the EBI manual.

Please understand that on the AT91RM9200 you have two sets of addresses: logical, seen by the code and physical, seen by the bus hardware. The memory mapping unit converts between these two sets.

You need to battery power the clock power line.

Or 1 bit mode if you have data flash.

What wrong with writing data to flash, upon power down?

And all processor states and registers.

I guess i dont know what pin is the clock power line. Is it the cor voltage ?

Ok, on the state of the machine during power cycle. I just need to remember some user memory that is updated alot, so flas wouldnt work, thus the SRAM.

Am I screwing up by not having 32 bit dynamic memory ? I really dont wan to bog the system down that much. Will I be glad in the end that i installed the dynamic memory ?

I dont see where the address boundaries get set for the CS0-CS7 in th SMC. Gee Whiz I really need to understand the chip selects, and it looked to m that the chip select boundaries were hardwired for 64Mbyte pages ?

COuld You enlighten me on this, I am new to this processor.

Thanks Alot, John

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Not sure if it is from VDDCORE or VDDOSC. You need to hook up both anyway. In standby mode, the processor draw 3mA from VDDCORE.

If you need more memory, SDRAM would be cheaper.

Yes, all CS are 64M pages. That why you need the MMU.