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MPMC3, DDR 32Mx16, S3E1200, single bank, impossible?

Hi all,

I wonder if it possible to make a MIG1.73 compliant design by connecting 32Mx16 DDR SDRAM to a single bank on a FG320 Spartan3E1200? Btw MIG1.73 compliance is a must for using the MPMC3 memory controller in EDK9.2.

Unfortunatelly the MIG coregen does not allow to put all of the DDR pins in a single bank. Since we have a very good example that this is possible - Spartan3E Starter Kit uses only bank3, I wonder how to replicate this design in MIG coregen?

Is it the ony way to accomplish that by using the Spartan3E Starter Kit pinout or are there other solutions?

Cheers,

Ales

Reply to
Guru
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It wasn't a problem in MIG 1.5, and when MIG 1.6 came out, I verified that it generated a ucf with the same pinouts as MIG1.5. I haven't tried MIG 1.7.

--
Joe Samson
Pixel Velocity
Reply to
Joseph Samson

Hi Joe,

Aren't you using Virtex series? It is more suitable for MIG phy I think.

The problem with this particular Spartan3E package is that banks 1 and

3 have just enough pins (except for calibration loop) for 32Mx16 DDR, but MIG does not want to use them (it forces clocks to bank 0 and 2). If I follow MIG guidelines then I loose another bank - it should be connected to 2.5V.

I have never used MIG before and I do not know how to surpass these limitations. Any help is welcome.

Cheers,

Ales

Reply to
Guru

This product is on Spartan 3E 1600, but the original work was using the

1200.

Which clocks do you mean - a master oscillator input? MIG wants that on bank 0 or 2 because those have the global clock inputs. Bank 3's LHCLK local clocks will only supply the left hand side of the chip. The global clocks supply the entire chip. I suppose that you could generate a design that had the pinouts that you like in Bank 3, then investigate modding the code to use a LHCLK input. In the design that MIG1.5 generated, LHCLK1 was unused.

There are lots of oscillators available; there is probably one that supports the standard that you want for bank 0 or 2.

--
Joe
Reply to
Joseph Samson

Thank for info Joe,

Pixel Velocity using a Spartan - are you entering a low cost market?

A master oscillator input is in bank 2 (GCLK0). I do not trust HCLKs. I was referring to DDR differential clock which should be in bank1 as other DDR signals.

My problem is actually MIG methodology - how to build a custom design?

Input clock is not a problem, but If I put other DDR pins there, then the bank should be 2.5V powered.

Cheers,

Ales

Reply to
Guru

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