Hi,
Lets say we have a signal crossing from a high frequency clock domain into a low frequency clock domain, where the low frequency domain frequency is very low, say 32kHz. Is there any point in having a double flip-flop synchronizer here, given that the frequency is so low? Shouldn't a single flop be good enough?
Cheers, Jon
No.
Yes.
It sounds like a weird setup. Are you sure you need a 32kHz domain? BTW., There's a school of thought that metastability can manifest itself as runt pulses. But you wouldn't use the output from the 32kHz FF to clock anything, would you? (Answer NO!) :-) HTH, Syms.
The problem is that the slow clock will miss the narrow pulses most of the time. I would run all of the logic using the fast clock and synchronize the slow pulses to that.
-- Mike Treseler
As long as there is a *single* flop to synchronize the signal, only one flop is needed. The design must not have more than one register that depends on the live signal. Once synchronized, the rare addition of 1-3 ns will not be a problem for downstream logic.
This is not an issue.
Not really possible as the idea is to save power.
Cheers though, Jon
Yes. Low power design with a wakeup timer running of 32khz crystal.
No :-)
Cheers, Jon
That's what I was thinking. Thanks.
Jon
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