Hi,
I have two clock domains in my Verilog design (Spartan2), 33 MHz and 20 MHz. My problem: data transport between domains create deadlock. (When I use the same clock in all domains, this send/receive primitive works fine, but I need different clocks...) Can somebody help me? URL, FAQ, RTFM? :)
Thanks, BB
// send @ 33 MHz data_reg = 4; data_ready
I don't exactly know what you want to do but maybe this could be helpful. Read this: At
Patrik Eriksson
MHz.
Your circuit is (approximately) Weinstein's Flancter. Read the details in this URL:
A couple of questions:
1) did you remember to initialise data_ready and last_data_ready?2) did you stop the 33MHz side from sending, by having it look at the value of last_data_ready? If you send two values, then data_ready will toggle twice and the 20MHz side will not see it.
HTH
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