Hi everyone,
I tried to figure this one out myself but it turns out not so easy for someone with this lack of experience like mine. I'm writing a PC app that will issue JTAG commands over paralell port to some unspecific FPGA at the moment, running let's say some cipher algorithm. I want to use my app to set input levels with JTAG and observe how it changes output signals. In order to impose signal levels over JTAG with my application I have to somehow "halt" the main FPGA clock if I want to do it in an exact moment and here's my question: is the FPGA clock stopped when TAP controller is in some specific state, concerning JTAG BSR operations or do I have to do it myself (how-to?) ?
Thanx in advance! Chris