Interfacing EDK application code with Specific BRAMs on FPGA

snipped-for-privacy@gmail.com schrieb:

you have put an ASIC on top of the FPGA !?

if the ASIC is on FPGA then well, is it wireless ASIC, or is the ASIC connected to the FPGA somehow?

If the ASIC has connection to the FPGA pins then you need some interface to the ASIC, the question about BRAM seems ir-relevant. What you need is some external interface, that depends on the ASIC you need to communicate with..

as of "specific BRAM" - it usually does not matter what instance of BRAM is used, they BRAMs are LOCed automatically, so you do not need to worry about them usually. Or what you mean by specific BRAM ??

or maybe you wanted to ask something else ?

Antti

Hello Antii,

I shd have been more clear on that. By ASIC I mean I have a RTL level code implemented in ISE on the FPGA fabric. Now this RTL code uses some BRAMs as for data access and this data is provided by the On-board DDR SDRAM, with the BRAMs acting as buffers. I m interfacing the DDR memory using the EDK with PPC acting as the IO processor. What I want to do is to write the data from the DDR memory to the BRAM and let the RTL code on the FPGA pick up the data from the "same" BRAM.

Thanks, Koustav

just add some BRAM controller and wire the second port to user logic and you are done.

antti

Hello Antti,

Can you provide me some example code snippet of the same? How can I make, sort of, a "global" block ram and let EDK and ISE refer to the same block ram. The BRAM will act as a FIFO with DDR controller of EDK being the source and the user logic in ISE being the consumer but both accessing the "same" BRAM.

Thanks, Koustav