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Initialisation of two dimensional array to known non-zero values in verilog

To declare and initialise a one-bit register in verilog we use the following statement reg one_bit_reg=1'b0;

Similarly, to declare and initialise a one dimension reg (e.g. 8-bit) we can write reg [7:0] reg_len_8=8'd0;

We can declare a two dimensional array (e.g. 16x8-bit) as reg [7:0] reg_dim_2 [15:0];

But how can we initialise this array in the same statement? or How do we declare the initial state (known non-zero values) of an array without using extra logic (especially when implementing on hardware (FPGAs))?

Reply to
sudheer
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For simulation purposes, you may use an init loop:

initeger i; init for (i=0;i

Reply to
Kevin Neilson

Adtually, the statement:

initial $readmemh(reg_dim2,"init_file.txt");

Should wordk for synthesis and simulation. At least, xst claims to support it, and all simulators support it.

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Reply to
Stephen Williams

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