How to obtain original input/output signal name from SDF Timing Simulation within Modelsim?

Maybe you are using a component instance, and need a configuration. Here's an example: ____________________________________________

-- vital entity by place+route

-- vho = /usr0/tres/vhdl/xszero/synth/work configuration vital of test_xszero is for sim for dut:socket use entity vho.xszero(\ep1k50fc256-1\); end for; end for; end configuration vital; ______________________________________________

Or maybe you haven't written a vhdl testbench yet. It is signals from the testbench architecture. that drive your design instance.

-- Mike Treseler

When simulating .sdf in Modelsim, I can see the registered signal names of my VHDL description apart from many other gate level names.

Should I not be able to see the "original" registered names?

Thank you.

Kind regards

At first thanks for Mike's answer. But my exact question was how to extract so many many internal signals which are listed during the timing simulation. For example, _inbuf, _ibuf, _gst, etc. How can I know which signal represents my original input signal or output signal?

The job of synthesis is to create a netlist of primitives (like dffe, inbuf etc. ) that sims the same as your code. You can view the netlist on tools like leonardo. I don't know of any way to relate primitives to your source code.

Normally synthesis "just works". When it doesn't consider the following.

1. Double check the static timing report and synthesis warnings.
2. Eliminate asynchronous processes and multiple clocks.
3. Double check all inputs for synchronization.
4. Break the design into pieces zoom in on the problem.

Good luck,

-- Mike Treseler