Dear Group,
I know how annoying it is when one posts blocks of HDL, but I would really appreciate someone telling me why this code does not work -- or at least, a pointer to my stupidity!!!
This HDL is supposed to generate standard -ve syncs plus an early 'newline' signal to a specialised SDRAM controller which writes a complete line of octets into alternate block-RAMs in my Spartan-3 device.
It then attempts to display them by generating alternate read enables (based on the current vertical line).
Tomorrow I am going to rewrite the code using discrete processes (one for each sync signal etc...).
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.numeric_std.all;
entity VidCont is generic( DATA_WIDTH : natural := 16; -- video data width VADDR_WIDTH : natural := 10 -- Video FIFO (blockRAM) address width ); port( -- Interface clk : in std_logic; -- Master clock @25MHz rst : in std_logic; -- Reset -- Video blockRAM side VIAddr : out std_logic_vector(VADDR_WIDTH-1 downto 0);
-- Video line buffer address VADIn : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- Data from 'A' block RAM VEnA : out std_logic; -- Enable 'A' FIFO VBDIn : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- Data from 'B' block RAM VEnB : out std_logic; -- Enable 'B' FIFO NewLine : out std_logic; -- Initiate line read burst -- TFT interface VRed : out std_logic_vector(5 downto 0); -- 6-bit red VGreen : out std_logic_vector(5 downto 0); -- 6-bit green VBlue : out std_logic_Vector(5 downto 0); -- 6-bit blue VDE : out std_logic; -- Data-enable VVSync : out std_logic; -- Vertical synch. VHSync : out std_logic; -- Horizontal synch. -- Debug signal... Debug : out std_logic ); end VidCont;
architecture arch of VidCont is
constant YES : std_logic := '1'; constant NO : std_logic := '0'; constant HI : std_logic := '1'; constant LO : std_logic := '0'; constant ONE : std_logic := '1'; constant ZERO : std_logic := '0';
-- TFT timing parameters... constant tHP : natural := 800; -- Horizontal sync. period constant tWH : natural := 96; -- Horizontal sync. width constant tVP : natural := 525; -- Vertical sync. period constant tWV : natural := 2; -- Vertical sync. width constant tHV : natural := 640; -- Active horizontal period constant tHBP : natural := tWH+40; -- End of H back porch (start of active area) constant tHFP : natural := tHBP+tHV; -- Start of H front porch (end of active area) constant tVV : natural := 480; -- Active vertical period constant tVBP : natural := tWV+33; -- End of V back porch (start of active area) constant tVFP : natural := tVBP+tVV; -- Start of V front porch (end of active area)
-- Horizontal & vertical counters... signal hCount_x, hCount_r : natural range 0 to tHP+1; -- Horizontal column count signal vCount_x, vCount_r : natural range 0 to tVP+1; -- Address counters... signal hAddr_x, hAddr_r : std_logic_vector(VIAddr'range); -- Horizontal address -- Data enable flags... signal hDEm3_x, hDEm3_r : std_logic; -- Early (-3) horizontal data enable signal hDEm2_r : std_logic; -- Early (-2) latched horizontal data enable signal hDEm1_r : std_logic; -- Early (-1) latched horizontal data enable signal hDE_r : std_logic; -- Horizontal data enable signal vDEm2_x, vDEm2_r : std_logic; -- Early (-2) vertical data enable signal vDEm1_r : std_logic; -- Early (-1) vertical data enable signal vDE_r : std_logic; -- Vertical data enable signal nlBurst_x, nlBurst_r : std_logic; -- Newline burst strobe signal IVEnA_x, IVEnA_r : std_logic; -- Block RAM 'A' read enable signal IVEnB_x, IVEnB_r : std_logic; -- Block RAM 'B' read enable -- Syncs... signal IVSync_x, IVSync_r : std_logic; -- Vertical sync signal IHSync_x, IHSync_r : std_logic; -- Horizontal sync signal AltLine_x, AltLine_r : std_logic; -- Source flipper -- RGB data... signal RGB_x, RGB_r : std_logic_vector(VADIn'range); -- Demultiplexed and latched RGB data
begin
-- Attach signals to outputs... VIAddr