Hi I was wondering if anyone here can help me.
I need to infer a true dual port BRAM with seperate clk, addr, data, en and wr lines on a Spartan-3 device but according to the XST manual this is not supported and after googling for a couple of days I've come to a dead end.
I need this in order to provide an external memory interface to some shared memory and the design is so simple and clean at the moment that I really want avoid having to use an async FIFO which would need alot of re-jigging to the upper levels and make things quite ugly.
Does anyone know if this is even possible with the free ISE Webpack tools? Or will it require me buying some other software? This is my first FPGA design and is more of a hobby that may have some commercial potential so I cant really justify spending lots of $$$ for something I may only require the use of once.
Many thanks in advance.