dual-write port BRAM with XST/Webpack

Kotek Barajazz · 2004-11-27T15:42:40+00:00

Hi I was wondering if anyone here can help me. I need to infer a true dual port BRAM with seperate clk, addr, data,en and wr lines on a Spartan-3 device but according to the XST manualthis is not supported and after googling for a couple of days I'vecome to a dead end.I need this in order to provide an external memory interface to someshared memory and the design is so simple and clean at the moment thatI really want avoid having to use an async FIFO which would need alotof re-jigging to the upper levels and make things quite ugly.Does anyone know if this is even possible with the free ISE Webpacktools? Or will it require me buying some other software? This is myfirst FPGA design and is more of a hobby that may have some commercialpotential so I cant really justify spending lots of $$$ for somethingI may only require the use of once.Many thanks in advance.

Nov 27, 2004 21 Replies

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mike_treseler 21 years ago

I tested it. Leo/Xilinx can't handle the second write enable. Quartus/Stratix runs a synthesis, but does not infer dp_ram.

-- Mike Treseler

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rickman 21 years ago

Damn good question. I suggest you ask your synthesis vendor...

Oh, BTW, if you really want to deal with spammers, you might check up on a Maryland company that is going after them big time.

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I am in Maryland and I would love to be able to cash in on this.

Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX

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