Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?

everything is possible, and the impossible becomes possible - when you do it.

Antti

Just do it!.

Of course I am trying to do it, but any help is very grateful at least for someone like me.

At the moment I am trying to use this core without any modification, but anything works at the first time. That is the reason why I look for help while I am working with it.

Anyway, thanks for the answer. It is a very philosophical phrase.I thinkthat I am going to copy it.

Regards Pablo

;) gee.

the thing is that getting some DDR memory IP to working on platform XYZ may require more work then just changing clock feadback. you should not expect some one todo this for you, unless its paid contract work.

the memory cores sometimes work out of box, sometimes it maybe months of hard fight to get them working.

Example

Xilinx DDR IP Core.

you route clock feadback to clock capable io xxxx_N you get NO ERROR REPORT, all time is fine, you look all path in FPGA editor, everything is 100% fine. but the DDR memory core just DOES NOT WORK.

now you change the clock feadback to IOPAD xxxx_P, and everything works. but there is no noticeable difference in any routing or timing reports.

of course, if you read Xilinx datasheets, then you also can see that you MUST use _P pad.

but there are many ways to obtain this kind of knowledge. some of them are hard and painful.

and our mileage may vary a great deal. my toys at age of 1.5 (in 1967) where metal can GE transistors, so its long path behind.

thats why I take the freedom to be sometimes little philosofical, in replies to deep technical questions.

Antti some more wisdom from me (had to use web.archive as domain is expired)

expired)

I don't expect that someone does this for me. I only request for some help. I have some idea about how try to solve it but at the moment I am trying to implement a project with this core and a basic vhdl file to read and write in memory. Then if this doesn't work I would try some ideas to do it.

This vhdl basic file is what I don't know how to build it. BUt I suppose most people has already done this and I request for their help in which experiencies has taken.

PD: Sorry for my English, it is not as perfect as I wish.

To finish this topic I want to say that if I request for some help is because I help to anyone who want to ask me.

Once again, thanks for answer me and sorry if my question has bothered you.

Regards Pablo

expired)

you should not assume "most people have done xxx" you should not assume anything ;) as all assumptions tend to be false

instead of "trying to learn" to be able "todo" things, start DOING them, you will learn on the way.

Antti