Data width in Block ram

Available widths are 1,2,4,8,9,16,18,32 and 36bits - 9, 18 and 36bits widths are achieved by using parity bits.

To achieve high speeds and and area efficiency, BRAMs are built as SRAMs and come with similar row-column organization that places some restrictions on how freely bits can be accessed. If you use 8, 16 or 32 bits, you waste the parity bits. If you use 9, 18 or 36bits, you can use every bit within the BRAM. For any other width not listed in the first paragraph, you will be wasting bits up to the next widest width.

-------------------------------------------------- Thanks. But Xilinx2P doesn't support this function, does it? I found it in Xilinx-4/5

Have you seen or used the inferred RAM/ROM in the Xilinx Toolbox?

Huh?

The V2P's BRAM design has been inherited by the Spartan 3 and Virtex 4... the only difference is that the V4 adds read-before-write, byte enables on writes and wraps BRAMs in an optional (and quirky) FIFO hard-macro. Other than that, they are all practically the same. The V5 BRAMs push BRAM capacity to 36kbits (but can still be operated as two completely independent V2P/S3/V4-like halves), add support for 64/72bits widths, ECC and fully functional (no known quirks yet) FIFO hard-macros.

XST does not support inferring BRAMs with asymmetric port widths but this can be worked around of by using direct instantiation, you just need to find the necessary entity name and port map. If all you want is a BRAM with all same-width port, simply lookup XST's coding style guide for the coding templates. I have done it many times with ISE 8.1/8.2 and have been mostly successful.