When I used coregen to create a DCM it provided the simulation code in verilog (ISE 8.1). My old projects in 7.x created these in VHDL. Is there a way to select which code type is created? I do everything in VHDL.
Thanks, Joel
Hi Joel, Goto Project->Project Options->Generation in Coregen. There is a "Design Entry" option in which you can choose between Verilog and VHDL code generation.
Regards, Srini.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.