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CLOCK_SIGNAL Constraint.

Hi everybody...

I m deriving 4 clocks in my module, are all gated with respect to a synchronous individual clock enable signals. I m using this module as a sub module for my toplevel design. While running PAR for the sub module i m not getting any messages regarding CLOCK_SIGNAL constraint, but if i run PAR for the toplevel in ISE 6.2.03i, it is displaying "Please use CLOCK_SIGNAL constraint....". I tried and tired applying the constraints several ways, but there is no change. All these clocks are of different frequency and have different clock enable signals. Please help me to find a solution for this problem.

Thanks in advance.

Regards... Chandu

Reply to
Chandrasekhar
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Using gated clocks in FPGAs is generally a bad idea. Besically, the hardware doesn't support it. (neither does the software)

Try using the gating term as an enable on the FFs instead.

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Reply to
Hal Murray

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