Power supply Decoupling requirements

You don't really calculate anything, you just follow best practice design rules. For each device in your design read the datasheet and app notes to see what they recommend. Many big (FPGAs for instance) and high speed devices have very specific requirements, they will tell you all about in the datasheets and app notes. Disobey manufacturers recommendations at your own peril. If nothing is mentioned then it's probably not that critical, in which case you'd genrally use a single 10nF cap for each device if you have the room and cost budget available, just to be safe. Although you can probaly get away with big power planes and the distributed capacitance in a lot of cases, with just a few caps sprinkled over the place in the more critical areas.

I'm sure other will elaborate further on the general concept of decoupling, and there is plenty of info out there on it, Google is your friend. Suffice it to say that decoupling is a bit of a "black art" and there are no hard and fast rules that work every time, every design will have different requirements. Follow general guidelines and you will usually be fine.

Dave :)

Well, you can calculate it (at least to a decent first approximation), but you have to keep ESR, ESL and Z(f) all in mind.

In some very high speed systems, there are specific known frequencies that will occur. The OP doesn't give enough details to help on that, though.

The last *really* highspeed system I designed was set for DDR Infiniband (the switch board had 384 5Gb/s diff pairs ;) and the decoupling was primarily for the logic clock in the switches (at least around those devices) and appropriate harmonics. [The backplane had

2304 IB pairs apart from any other signals]. I decoupled the IB signal noise by series ferrites along with caps, and the IO buffers had their own power - the outputs were CML which made life a little bit easier.

For a first approximation for decoupling (at least to see what Z has to be) I get the effective local impedance of the power system (simply Vchip / Ichip) and divide by 10 - that's the max impedance I want to see in the decoupling system to ground for capacitive decoupling. For a high current, low voltage device (pretty typical in a highspeed environment), that can make decoupling quite an interesting exercise.

For a 1.2V, 12A device (which is pretty close to what I was using) that yields 10 milli ohm effective impedance max for that device (at the various frequencies of interest) requirement for decent decoupling. It's not incredibly scientific, but it gives me an idea of what I am looking at. On really highspeed stuff, I also make a distributed decoupler by having the local power and ground for a device on adjacent planes, and in a high layer count board, that can yield some pretty effective decoupling.

Given that decoupling at high frequencies is a very localised affair, this trick works and I am aware it's hardly thoroughly scientific.

Much depends on just what the OP considers 'high speed', of course.

Cheers

PeteS

Current flows in loops, the higher the frequency the more important it is to keep the loop small. The decoupling capacitors value isnt very important, it's location is, by keeping the capacitor close to the chip you keep the current loop for that chip small.

The decoupling capacitors provide the charge required by logic to switch states. In order to do this effectively, without causing disturbances or fluctuations in the power or ground voltage levels, it is necessary to have a low impedance path for the power and ground connections over the frequency bandwidth where your signals will have significant engery.

As a rule of thumb, unless datahseets or some other piece of information direct me otherwise, I tend to use 0.1uF or .01uF caps for most decoupling. For slower logic and analog often times I will use

0.1uF to 1.0uF. A lot of it comes down more to art than science.

As I said above, you should keep in mind the bandwidth of the digitial signals that you are trying to provide a (low impedance) power system for. Another rule of thumb I use for this is that the band of interest is upto about .5 / Rise time(in Nanonseconds). If for example, a digital signal has a rise time of 2ns, it will have significant engery content upto about 250Mhz. You will want to make sure that your power system can handle this frequency range.

Be sure to check the datasheets for the capacitors you are thinking of using and make sure that it is low ESR and ESL and doesn't self resonate (start to behave like an inductor instead of a capacitor) in the frequency band you need to bypass. Typically ceramic SMT capacitors are a good, but not the only choice. Except for perhaps a bulk decoupling cap at the power supply you should probably stay away from aluminum electrolytics for decoupling.

Decoupling is more an art than a science.

Basically you want to have the lowest possible impedance across the power supply pins of the power-drawing component.

But you can't just plunk a 100uF capacitor across pins 7 and 16 or whichever! The bigger the capacitor, the lower its self-resonant frequency. A 100uF capacitor with 1/2 inch leads is going to resonate somewhere around 200KHz to 1MHz, making it act very non-capacitor-like around that frequency. So you have to go with the smallest capacitor that will still be capacitor like at the highest frequency of interest, AND still be large enough to have a low impedance at low frequencies. If those are irreconcileable, you can always use a BIG capacitor to handle the low end, and one or more smaller capacitors to handle the high end.

Just to confuse things, there's one school of thought that says you SHOULDNT use really good capacitors, as they're just going to resonate at SOME frequency. Perhaps better is to have a capacitor feeding a resistor, said resistor will damp the Q of the resonances and absorb the glitch power.

I most definitely agree, but we can stack the deck in our favour a little :)

There are so many issues, some of which only raise their heads at high speed. A typical 100uF cap (even a ceramic, and there are such things) will not have particularly good high frequency performance, but for bulk storage (for the benefit of the OP, that's a large amount of charge that may be provided to the decoupled circuit to account for large changes in current the supply can not necessarily handle) they're great.

Once you get above the skin effect knee (typically 75MHz or so for a 8 thou track on 0.5 oz cu) the physical case size and type becomes important too. 0306 decoupling devices (as opposed to 0603) have lower ESL and may be preferred where an 0402 may not be available for a given capacitance. The higher the frequency, the more important physical dimensions become, as does distance from the device to the chip it's decoupling.

So there's a huge amount of art (as always in engineering, it's a matter of 'it depends') in choosing decouplers.

Cheers

PeteS

For most applications following the guidelines on this Lattice Semi note will be adequate

$CF$98$5

However, for stringent applications such as RAMBus memory where signal voltage swings of 200mV at data rates above 3.2GHz are involved, the decoupling requirements may be more specialised and modelling may be necessary.... not something many have the means to perform though.

Fine,

the think what iam following is one 0.01uf for each power supply pin of the Ic and one Tantulam 10uf for four 0.01uf capacitors. Is it OK ?