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PLL Lock to an Offset Frequency

The obvious answer, which is to design a PLL running at nominally

512MHz and divide this output by 63, 64 or 65, is practicable, but not all that easy, and doesn't give you exactly the frequencies you want.

The alternative version of this strategy is to run your phase-locked loop at 8.125MHz and use binary rate multipliers (SN7497 - the HCF4089 isn't fast enough) to steal one or two pulses of every sixty four from the 8.125MHz clock stream. Unfortunately, the 8.0MHz and 7.875MHz pulse streams then have rather odd-looking Fourier transforms and would not be acceptable as clock sources in many applications.

You can get rid of this particular problem by running your PLL at

520MHz and dividing all three output streams by 64, but then you have to realise your binary rate multiplier in some fast chunk of programmable logic. This is practicable, but not easy, though it does have the advantage of giving you exactly the frequencies you want.

The practical way of doing it is to buy two Analog Devices DDS chips, and use one as the oscillator in a digitally controlled phase-locked loop, and program the other to track it's output frequency with a fixed

125kHz offset - positive or negative as you choose.

That would be a perfectly practical homework problem, of the sort modern academics love, because all the difficult and interesting stuff that make real phase-locked loops such a swine to design and build gets realised in the digital domain, where everything is much closer to ideal.

----------- Bill Sloman, Nijmegen

Reply to
bill.sloman
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Hi I want to design a PLL which must lock to a frequncy which is a bit different from input frequency. For example input Frequncy is 8MHz and PLL must synthisize a 8.125.000Hz or 7.875.000Hz (8MHz+- 125KHz) output signal.

How can i do this?

Hanse Hashemi

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Reply to
hashemi7102

Divide 8MHz by 64 for reference input (125KHz) then use div63 or div65 in the feedback.

OR:

Use a single-sideband mixer to mix 125KHz with 8MHz.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

Nice scheme - much better than my first two proposals, but a vile description.

Your idea seems to be that you have two voltage controlled oscillators, in two linked phase locked loops. The first oscillator is running at

8MHz, which the first phase-locked loop locks directly to the 8MHz input. The output from the first VCO is also divided down by 640 to provide a 12.5kHz reference waveform, which happens to be phase-locked back to the 8MHz input.

You then set up the second voltage-controlled oscillator to run at a different frequency - say 7.875MHz = which you divide down by 630, to provide a second nominally 12.5kHz signal.

You then use a second phase sensitive detector to compare the two

12.5kHz signals, and drive the second - nominally 7.875MHz - VCO to force the two 12.5kHz outputs into lock. This second phase locked loop thus indirectly synchronises the 7.875MHz oscillator to the 8MHz input.

You frequency difference is 1/64th of the input frequency, rather than an absolute 125kHz, but in all other respects this strikes me as a perfect solution.

Not as easy to realise as my third solution - a digital phase locked loop built around a pair of DDS chips, which could deliver an absolute frequency offset, if that was what you wanted, but probably much cheaper.

-------------- Bill Sloman, Nijmegen

Reply to
bill.sloman

Assuming a low-noise input signal a 3-state phase/frequency detector, like the phase detector II in the 4046 or that ELC part that Jim will shortly tell you about makes a good alternative.

Mix your oscillator signal with your input; the "up" (or "down") pin on the phase detector will pulse with energy at f_osc + f_signal and f_osc

- f_signal. The nice thing is that only _one_ pin will pulse; the other one will stay steady. If your oscillator frequency is on the wrong side of your signal the wrong pin will pulse and the right pin will stay steady, so you'll be able to drive your loop in the correct direction. Low-pass filter the appropriate pin, square it up with a comparator, and apply it to another suitable phase detector with 125kHz as a reference.

If you use the 4046 for this both the "up" and "down" signals are brought out to the same pin (13). You'll have to pull pin 13 high or low with a resistor and square it up with an inverter before you filter it.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Reply to
Tim Wescott

Huh? A PFD isn't asymmetric.

Reread my first example: 65/64*8MHz = 8.125MHz, 63/64*8MHz = 7.875MHz

My second example, elaborating: 8MHz/64 = 125KHz, then MIX in an SSB mixer to get the +/- desired. No PLL needed, just some phase shifters ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

-snip-

I think he means that a PFD will give output on only one pin when the frequencies differ -- you have to get close to lock or otherwise have the two signal frequencies swimming around each other before both pins become active.

-snip again-

True, but image-reject mixers can be tricky and filtering methods aren't very frequency-agile. If you want both the input frequency and the offset to vary by much it would be easier to do it with phase-frequency detection.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Reply to
Tim Wescott

True, but the OP was (presumably) a fixed input frequency and (again presumably) selectable output frequency.

I did one this past year for a WiFi chip (924MHz/1188MHz) using SSB, which is what the customer wanted. But I think, in retrospect, I'd talk the customer into a PLL next time around. I think it'd take up less silicon real estate.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

Not on either side of zero phase it isn't... it's linear thru zero. With a PFD you could care less about ±pi.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

-snip-

Customer: "I want you to build me a big gun, to be lined up with my right thigh per this here drawing and fired into the ground".

You: "You want to shoot yourself in the foot?!?"

Customer: "No, I want to quickly and efficiently make holes in the ground. Geez."

You: "But your foot is in the way! Look at your own drawing!"

Customer: "Don't be a barrier to progress! Just build the damn thing and bill me!"

You: "Well, if you insist..."

(later)

Customer: "Hey! Your equipment is a piece of xxxx and my foot hurts really bad!"

This is worse when your customer is also your boss, which is why I'm now a consultant...

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Reply to
Tim Wescott
[snip]

I decided that in 1973 ;-)

...Jim Thompson

-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | |

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| 1962 | I love to cook with wine. Sometimes I even put it in the food.

Reply to
Jim Thompson

If you use a frequency-phase detector or other very asymmetric PD, you don't even have to use an SSB mixer, because the unwanted null is unstable. On each sideband, one null is unstable because of the sign of the loop gain. On both sidebands, the null at +- pi is unstable because of huge loop gain. Only one of the four nulls is stable.

Cheers,

Phil Hobbs

Reply to
Phil Hobbs

Amplitude modulating the input source, and filtering out the carrie?r

Reply to
Ian Stirling

Aha! Now I see our miscommunication. You said, "If you use a

**frequency-phase detector** or other very asymmetric PD". An XOR is NOT a PFD (phase-frequency detector, AKA edge-matcher), it's a PD (phase detector, AKA MIXER). PFD's are used in synthesizers. I am co-inventor of the first PFD, the Motorola MC4044.

Huh? The OP wanted to **generate** either an upper or lower sideband. An XOR mixer isn't going to do that.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

Hi,

8.000MHz divided by 64 = 0.125MHz 7.875MHz divided by 63 = 0.125MHz 8.125MHz divided by 65 = 0.125MHz

Try a conventional PLL with the appropriate M(64) and N(63/65) dividers using a couple of down-counters such as the 74HCT40103 and a 4046-like chip (IMHO the 74HCT9046 is the better one).

Cheers - Joe

Reply to
Joe McElvenney

The traditional way is to first determine the increment in offset frequency say 12.5KHz, then this is 8MHz/N where N=640, set this as the PLL reference input. Then for an output frequency in the range 7.875MHz to 8.125MHz, this is a range of multiplication of 630 to 650 of the

12.5KHz reference, which means you place a programmable divider in the range 630 to 650 in the feedback path from the VCO to the other phase detector input of the PLL. Then the PLL output can be stepped in that range of output frequencies with 12.5KHz increments. If you only want the two frequencies 8+/- 0.125MHZ the set N=64 for a 125KHz reference frequency, and the divider in the feedback loop switches between 7.875MHz/0.125=63 and 8.125MHz/0.125=65. For a contiuous adjustment is offset frequency between this to limits, there is the dual modulous PLL, and this entails, the same setup with the 8MHz divided by 64 driving the PLL reference input, the programmable counter switching between divide by 63 and divide by 64 in the feedback path, but now now you mix the 8MHz input with VCO output, low pass filter to extract offset frequency, frequency detect that with a digital phase/frequency detector against your offset reference, low pass filter, analog compare that against null, and use comparator to set PLL programmable feedback divider to /63 if VCO output is high, or to /65 if VCO offset is low. If you need instantaneous switching then most of this applies but you may need to switch between to PLLs- is this and FSK application? Your frequencies are low enough to use a 74HCT4046.
Reply to
Fred Bloggs

Unbelievable illiterate post! This is what happens when visualizing schematics while writing...

Reply to
Fred Bloggs

Of course it's asymmetric. The voltage vs phase plot is a sawtooth.

Cheers,

Phil Hobbs

Reply to
Phil Hobbs

OK, Maybe I'm dense this afternoon (not that unusual for me :-). Explain on me how *exactly* you're getting from 8MHz to 8.125MHz using an XOR.

And the "Other people understood" please join in. Laughing at my density is allowed ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

I read in sci.electronics.design that Fred Bloggs wrote (in ) about 'PLL Lock to an Offset Frequency', on Fri, 14 Oct 2005:

Don't be too hard on yourself. It improves a lot with a few paragraphs applied. The typos become more easily interpreted, too.

--
Regards, John Woodgate, OOO - Own Opinions Only.
If everything has been designed, a god designed evolution by natural selection.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk
Reply to
John Woodgate

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