"multi-level bits"

I'm interested in increasing the transmission rate over Cat5 for a personal project. (Cat5/5e/6 will be chosen because of it's properties and obtainability but will not be used in the standard way)

In any case what I'm interested in using a "multi-level bits" per clock of transmission. Digital communication almost always uses a single bit per clock.

For example, using a single bit(0 or V) in cat5 at 100mHz allows only for a 100Mbits data rate. Using 4 bits allows for and effective rate of 400Mbits/TP(or over Cat6a, 2GB/TP). For my project this is significant.

Obviously adding more bits per clock increases complexity and decreases the noise immunity but I feel that it could be done with a few logic gates and will work for my particular application.

Since the signals will be differential it seems it may be pretty easy on the tx side by actually not having one of the lines being the mirror images but independent. Noise immunity will still be retained due to the differential nature.

Essentially on each end of the line we will have 4-bit DAC(for tx) and ADC(for rx) to convert to and from the multi-level representation.

My question is, besides the added cost and complexity(which doesn't seem to be all that great?), are there any other reasons why it is bad.

I conclude that there seems to be no loss of noise immunity:

Asymmetric differential signaling is used. External noise will be canceled out in exactly the same manner when symmetric different signaling is used(assuming that the noise does not depend on the voltage in the wire)

The noise margins can be kept the same by simply amplifying and attenuating the signal before and after transmission. e.g., normally

0-3.3v are used. We can amplify this to 0-26.4V which will give the same distance between each level(3.3V). Of course, the cost is 8 times the transmission power but this would probably be similar to when using a single-bit/clock rate that is 8 times larger.

Therefor, best I can decern, the real cost in achieving around an order of magnitude in throughput is a few dollars in parts. (a monolithic tx and rx ic would reduce the complexity to near 0).

Is there any real downside besides what I have listed. Basically what are the practical drawbacks?

Reply to
Jon
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  • Err..if the lines are not "mirror" image then they are NOT "differential nature".
Reply to
Robert Baer

I'm sorry but that is simply not true. The noise immunity comes from the fact that the noise is identical on both wires and when the two signals from the wires are subtracted the noise is cancelled out. This is regardless of what is input on both wires(before the noise takes effect). Very simple 3rd grade arithmetic shows this to be true. Symmetric differential signaling uses the mirrored signal only for convenience and simple mindedness NOT because it is required.

Reply to
Jon

You means a few high voltage FPGAs? Switching 16V to 20V at 100MHz will not be easy. The distance will also be much shorter.

Reply to
linnix

l not be easy.  The distance will also be much shorter.

huh?

The voltage translation would occur right at the wire after(and before on the rx end) anything else. It is simply used to increase the noise immunity in the wiring... nothing else. (it may not even be needed but is irrelevant to the problem of converting the single to and from a multi-level bit representation)

Reply to
Jon

ill not be easy.  The distance will also be much shorter.

You will need high speed, high voltage drivers to drive the wire.

Reply to
linnix

a

will not be easy.  The distance will also be much shorter.

100MHz voltage translators would not be easy to build. So, you have to do all the logics in high voltage.
Reply to
linnix

'Tis already being done commercially. The 1000BaseT standard "gigabit Ethernet" protocols use a 5-level pulse amplitude modulation scheme, operating at a rate of 125 megabaud on each pair (four pairs). Trellis coding is used to improve noise and crosstalk immunity.

My hunch is that your idea of carrying four bits per symbol, at those sorts of speeds, is likely to prove very difficult. That means you have to distinguish between 16 different voltage levels... you'll probably find that attenuations and signal reflections make it impossible to do this reliably in the field.

In practice, simply adopting 1000BaseT hardware may prove to be the easiest, least expensive, and most reliable solution.

--
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Reply to
Dave Platt

h a

Hz will not be easy.  The distance will also be much shorter.

e
t

do all the logics in high voltage.

I believe you are confused. You do not need to translate any voltages and the logic can be done at standard voltages.

Logic->DAC->Op amp->line->Op amp->ADC->Logic

Only the line will see "high voltage" and it is only used to increase interlevel noise immunity.

Reply to
Jon

Nope. We've been through this recently in this very boutique (search for "antenna" in the "resetting a filter" thread.

If the wires are driven differentially, the fields cancel at distant points, i.e. the pair is a transmission line.

If the wires are driven in phase, that's the same as a single wire, i.e. an antenna.

Driving or receiving asymmetrically, e.g. signal and ground, gives you a linear combination of the transmission line mode and the antenna mode, which will cause all sorts of grief.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

              AE6EO
r

That's what I've learned. It is being done. If I could get at the physical layer of 1000BaseT then it might work well. But basically I want to serialize a stream of bits with minimum latency as fast as possible without using packets and other such things. I'll have to look more into the 1000BaseT and see if I can find a way to use it.

Thx.

Reply to
Jon

How far do you plan to run? We're doing some baseband digital stuff at up to 125 MHz on CAT6 cable, up to 50 meters. The cable attenuation vs frequency and distance is complex, and varies between cables. Your enemy is ISI, intersymbol interference, namely leftover drool from past bits shifting the level of the bit you're trying to decode now. The usual answer is equalization.

--

John Larkin         Highland Technology, Inc 

jlarkin at highlandtechnology dot com 
http://www.highlandtechnology.com 

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom laser drivers and controllers 
Photonics and fiberoptic TTL data links 
VME thermocouple, LVDT, synchro   acquisition and simulation
Reply to
John Larkin

Huh?

Antenas?

What the heck does that have to do with anything?

Let a(t) be the input signal for one line and b(t) be the input signal for the other. Let n(t) be the common noise on both signals.

The "output" of the wire is A(t) and B(t)

then A(t) = a(t) + n(t) and B(t) = b(t) + n(t)

A(t) - B(t) = a(t) - b(t)

I.e. The noise is removed. (note, we could even have b(t) = 0 ==> single ended instead of differential but we have less noise immunity than if we set b(t) = -a(t))

This is regardless what a(t) and b(t) are. We can only recover the difference though. (in some sense, a(t) or b(t) but not both)

The issue is not so much as to use asymmetric differential signaling to decrease line noise symmetric differential signaling has better noise immunity due to cross talk between the twisted pair and a larger margin for line noise(2 times the amplitude). The main thing is that we can use the differences to help us map the voltages from 2 bits down to one

00 -> 0 10 -> 1 01 -> -1 11 -> 2

So here we will have 4 voltages levels per clock, the differential output at the rx side will receive 0,1,-1,2 which it will then map back to the 2 bit groups. This makes it way easier on the tx side at the cost of noise immunity(which will also change depending on the bits).

In this case each copper conductor only carries a voltage of 0 or 1. For more bits we must change that.

00 -> 0 10 -> 1 40 -> 4 01 -> -1 11 -> 2 41 -> 3 04 -> -4 14 -> -3 44 -> 8

In this case each conductor caries 6 possible voltages (0, 1, 2, 3, 4,

8) but all are unique. In this case it is a 3-bit system but requires another step of translation. There might be optimal mappings.
Reply to
Jon

.

It has to do with your receiver for asymmetric signals responding to both the differential (subtraction) signal AND the common-mode (sum) signal . If you're using only the difference, receiving (like Ethernet baseT receive rs) with a transformer coupling, you needn't drive nor filter against common-mode signals. But, if your signals are encoded into the common-mode, you CANNOT ignore them, you MUST drive that common-mode signal, and that makes your transmission line a potential radiator of electric waves (and a receiver as well).

Reply to
whit3rd

Further the better. At least 50m. CatX generally has 100m specs so it should be rather easy to achieve the data rates of these specs:

100Mbit rate/TP. I'm interested in increasing this if possible. 1000BaseT uses PAM-5 which but for some odd reason has the same data rates as non-PAM.

I can see how reflections could interfer with the multiple levels, which is why I suggested that pre-amplifying the signals might be required. This will offer the same interlevel voltage margins but, of course, might cause other problems.

Since it seems ethernet has already tackled the problem I'll have to do more research in that area. The main issue I have to contend with is having to use the physical layer. It's the only way to achieve the rates I'm after if I decide to use Ethernet...

Reply to
Jon

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But the common mode does not have any noise immunity?!?!?! So it would be useless to use TWP or differential signaling to do so?

What would be the real benefit of using the common mode of a differential TP over a single conductor? (by real benefit I do not mean increased cost, complexity, and marking hype)

Reply to
Jon

Only for sufficiently short wires. Once it gets anywhere near a quarter wavelength at your maximum signalling frequency, you're screwed. If you don't understand my comments about antennas, go ahead and try it. Alternatively, think about it like this: for a wire of any appreciable length, the even-mode signal radiates away and doesn't appear at the far end of the wire, leaving only the odd-mode signal.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

For the coding and decoding, you should get and read a textbook on data communication. The methods and their advantages and disadvantages are well known.

The speeds you specify mean that the cable has to be regarded as a transmission line. The signal travels principally in the isolation between the wires, and an asymmetric feed will convert your cable to an antenna spewing interference into the surrounding space and picking unwanted signals (interference and noise) to spoil your transfer. There is a good reason why there are symmetric transformers and balun coils in Ethernet interfaces.

Please note that the impedance of a twisted pair is around 100 ohms, so already 10 volts means significant power. The Ethernet standards are running at signal levels of the order of a volt. The attenuation of the cable chenges with frequency, and this has to be compensated, if you wish to be able to decode the received signal.

--

Tauno Voipio
Reply to
Tauno Voipio

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Ok, I looked up the term even and odd signals and I can see how it will be an issue. With multiple values the even and odd mode's are switch. In any case it shouldn't be a huge deal. First, Ethernet

1000BaseT already does this kind of switching and so the issues must have been worked out.

Second, one can still use symmetric differential signaling ==> odd mode by simply using a larger number of voltage levels.

for 3 bits:

000 -> (1, -1) 001 -> (2, -2) 010 -> (3, -3) 011 -> (4, -4) 100 -> (5, -5) 101 -> (6, -6) 110 -> (7, -7) 111 -> (8, -8)

(x,-y) means that an x level is sent on one conductor and y on the other(using some scale). This requires a larger number of voltage levels though which then introduces other problems which may or may not be more serious than what you have stated.

Reply to
Jon

You probably want to read up on phase/amplitude signalling. It was invented for telephone modems, but should generalise.

Essentially, your multi-level signal encodes data in terms of both phase and amplitude. You apply both in-phase and quadrature components to the driven end of the cable, and retrieve them from the receiving end.

--
Bill Sloman, Sydney
Reply to
Bill Sloman

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