Power MOSFETs have highly-nonlinear capacitances. For the new super-junction types, voltages 500V to 800V, nonlinearity can be severe, up to 100x. A new Coss spec, effective capacitance, comes in time related (tr) and energy related (er) forms, with a stated voltage, usually 80% of breakdown. It's a fixed capacitance that matches the FET's charging time or energy consumption. Older FET datasheets are missing these values. Anyway, I have created an instrument to measure these parameters and more, like Eoss vs drain voltage. For schematic and pcb layout, see DropBox link:
There are still other capacitance-measuring methods, _none_ of which really apply: "Energy equivalent" "Time related equivalent" (by CCS) "Time related equivalent" (by RC to 80%) "Hard switching equivalent" [*]
(I think it's IR who uses the RC method.)
Of course your circuit measures the energy parameter, and by measuring the risetime of the event (rail to rail, not 10-90%), you can get the CCS time equivalent as well. That's half of them!
[*] I don't think I've seen this anywhere. So I guess I invented it.
Explanation: consider that Superjunction capacitance acts like diode recovery, except over a span of 10s of volts, rather than ~1V. Consider an inductor switched across the transistor, from a constant voltage supply: at first, current will rise almost linearly with time (as the voltage creeps up), then as it leaves the high-C range, it explodes away with very fast dV/dt. As voltage crosses VDD, the inductance remains charged to some nonzero current, which is energy that must be minimized (if your layout can be made tight enough with respect to the switching speed of the transistors), or snubbed.
Because the inductor doesn't have the same (or complementary, I'm not sure) nonlinearity, one cannot use an energy argument here, to evaluate either the peak current or the risetime from existing manufacturer data.
In a typical application, the inductance being modeled, is the loop inductance of a half-bridge (high side - low side - supply bypass C).
This would give a reasonably accurate result for hard-switching risetime. For something like, say, an LLC induction heater[**], risetime would vary between the CCS equivalent case (soft switching, load current-commutated) and hard switching (under light load).
[**] An LLC converter might avoid hard switching, because it doesn't need a wide frequency range. So I'm just choosing this to be specific.
Anyway, I like the divider-cascoded-into-bottom solution. U3A seems kind of overkill, but I suppose a matched pair (Q16 plus a companion) wouldn't be accurate enough. (Hey what? That VR25000002005KA100 is only 10%! and there's no trim..?!) Similarly elsewhere, there's a lot of trim for offsets, but not for divider tolerances, by the looks of it.
Huh, PCAD.. ancient! ;) I don't suppose there's a color output mode, is there? It's hard to follow all the text boxes, net labels and component comments when they're all the same size, and packed so tightly on one sheet. (Alternately, can you do it on a bigger e.g. B or C sheet? I don't mean redraw the whole thing, just as a suggestion.)
Like, what's the difference between "SIG" and "Vx/150 SIG" ? Are they all the "SIG" net and "Vx/150" is just a label?
(And obligatory "Sloman should love it because it's got a 555". :^) Two of them even. A 556.)
Tim
--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: http://seventransistorlabs.com
"Winfield Hill" wrote in message
news:nejbp1048g@drn.newsguy.com...
>
> Power MOSFETs have highly-nonlinear capacitances.
> For the new super-junction types, voltages 500V
> to 800V, nonlinearity can be severe, up to 100x.
> A new Coss spec, effective capacitance, comes in
> time related (tr) and energy related (er) forms,
> with a stated voltage, usually 80% of breakdown.
> It's a fixed capacitance that matches the FET's
> charging time or energy consumption. Older FET
> datasheets are missing these values. Anyway,
> I have created an instrument to measure these
> parameters and more, like Eoss vs drain voltage.
> For schematic and pcb layout, see DropBox link:
> https://www.dropbox.com/sh/0r75g7tzy1yuqw8/AACVeaFZds1jb19D_fEfdwMha?dl=0
> Non-proprietary, sharing is OK. Comments please.
>
>
> --
> Thanks,
> - Win
Do the Spice models properly model these "highly-nonlinear capacitances"? ...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
The touchstone of liberalism is intolerance
I'm hoping CS RR gives close to the Coss(tr) value. But Coss(er) is more important.
I long ago made an instrument like that, IIUC. Run half-bridge run 10kHz, etc, no load, just plug in two DUTs, measure the power drain. Simple, useful. But I wanted more detail.
Just to point out right now my interest is not in switched inductors, but it's an important topic.
Correct, one current would be fixed, while the other drops to well below 1uA, so the opamp is necessary. It's important for low Vx values near 1.0V (10mV or so after dividing) to have low offset, because Coss changes so much near 0V.
Yep. I'll measure the caps before installing, thereby providing the necessary parasitic CAL data (opto-couplers, etc.). C0G doesn't have the DA soakage effect. I think a 1 or 2% measurement of the Vx voltage is more than good enough, provided the zero offset is low.
My PC CAD files are all under my PCAAD folder, but I long ago migrated to full Altium Designer.
It's B-size, and prints better on 11x17 paper.
My drawing is in color onscreen, with standard Protel colors (my PCB tech's original choice). I'll add a color version to the DropBox folder.
Yes, it's easier to see the difference between the PCB net-names, and notes or connector names, etc., if you have color image.
Yep! I like 555s, you get a flip flop, two comparators, and various other useful items. But I only use CMOS versions, thanks!
I would have said, no, but I found an example to the contrary. This Infineon link has a 49-page article by Anders Lind, with "support material".
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[What an insane link address!]
In that you'll find a spreadsheet with 800 Coss data points for SPA11N80C3 super-junction MOSFET. These Coss data points were extracted into Excel from the part's SPICE model, and they look petty close to the datasheet plot. The article has details. The SPICE model will be in my next post.
.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) Maux g2 c a a sw Maux2 b d g2 g2 sw Eaux c a d2 g2 1 Eaux2 d g2 d2 g2 -1 Cox b d2 3.66n .MODEL DGD D(M=1.2 CJO=3.66n VJ=0.5) Rpar b d2 1Meg Dgd a d2 DGD Rpar2 d2 a 10Meg Cgs g2 s2 1.22n
G_G1 d s VALUE={fpar27(V(d,s),V(g,s),Tref+limit(V(Tj),-200,999))} R1 g s 2G Rd01 d s 500Meg
G_G_Rd ldrd d VALUE {V(ldrd,d)/((dRd*0.5*(1+SQRT(1+4*(max(V(ldrd,d),0)/fpar15)**2)))
*((Tref+LIMIT(V(t1),-200,999))/fpar29)**fpar10)} R_R_ERd_g ldrd d 10k
G_Rdiod ldrd dio2 VALUE { V(ldrd,dio2)/(fpar14*((Tref+LIMIT(V(t1),-200,999))/fpar29)**1.5)} R_Rdiod ldrd dio 500Meg V_sense dio dio2 0
G_diode s dio VALUE={Ird(V(s,dio),Tref+LIMIT(V(t1),-200,999))} Rd02 s dio2 500Meg G_diode2 s dio2 VALUE={LIMIT(I(V_sense2),-1k,1k)-fpar26(V(dio2,s),Tref+LIMIT(V(t1),-200,999))}
C_pack dd g {w0} E_Edg1 d ox1 VALUE {V(d,g)-((exp(min((V(d,g)+Uoff)*x1,0))-y1)/x1+min((V(d,g)+Uoff),0))} C_Cdg1 ox1 g {w1} E_Edg2 d ox2 VALUE {V(d,g)-((exp(min(V(d,g)*x2,0))-1)/x2+min(V(d,g),0))} C_Cdg2 ox2 g {w2}
E_Eds1 dio2 dEQJ1 VALUE {V(dio2,s)-(exp(min(V(dio2,s)*x3,0))-1)/x3+min(V(dio2,s),0)} C_Cds1 s dEQJ1 {w3} E_Eds2 d dEQJ2 VALUE {V(d,s)-2*(SQRT(x6*limit(x6+V(d,s),0,2*fpar6))-x6)} C_Cds2 s dEQJ2 {w4} E_Eds3 dio2 dEQJ3 VALUE {V(dio2,s)-1/(1-x5)*(x7**x5*limit(x7+V(dio2,s),1e-6,2*fpar6)**(1-x5)-x7)} C_Cds3 s dEQJ3 {w5} E_Eds4 d dEQJ4 VALUE {V(d,s)-(w7*limit(V(d,s),(w7-w6)/sl,w7/sl)-sl*limit(V(d,s), +(w7-w6)/sl,w7/sl)**2/2-w6*max((w7-w6)/sl-V(d,s),0))/w6} C_Cds4 s dEQJ4 {w6}
E_Egs g sm VALUE {(0.5*((V(g,s)-k14)+SQRT((V(g,s)-k14)**2+deltb*0.3))-deltb*0.3)*Cox/(Cgs+Cox)} C_Cgs sm s {Cgs+Cox}
V_Isense dd ldrd 0
G_G_Ptot_channel 0 Tj VALUE {heat*LIMIT(V(d,s)*I(V_Isense),0,100k) } G_G_Ptot_Epi 0 t1 VALUE {heat*LIMIT(V(ldrd,d)*I(V_Isense),0,100k) }
*auxillary circuit for non-equilibirium diode charge
C_C001 a 0 {ta*td/(ta+td)} R_R001 a b 1 V_sense2 b fpar2 0 E_E001 fpar2 0 VALUE {-enable_diode*ta/td*I(V_sense)}
How well does that run on LTspice ?>:-} ...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
The touchstone of liberalism is intolerance
I design on PSpice... by client requirements, my models must run on LTspice... thus my back-handed comment >:-} ...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
The touchstone of liberalism is intolerance
Actually not the _client_, the client's _customers_ use LTspice. ...Jim Thompson
-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at
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| 1962 | The touchstone of liberalism is intolerance
I've got you one better ... if only in one specific case, I guess.
Some time ago, I was looking at the STW70N60M2 and related parts in the family.
I put it all in a spreadsheet, but it's really rather messy to release, so I'll speak to a screenshot instead:
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My interest was to create a SPICE model of the '70. The '24 (24A class) was available. Surely it's a simple matter of scaling up the terminal currents proportionally -- more or less?
So let's see how the 24 works. Hmm. Turns out, the SPICE model is in error by about 150%! This is illustrated as the blue curve in the energy plot (left middle), and the capacitance plot (right middle).
Meanwhile, I used SPICE's junction capacitance formula to approximate Coss, on whatever basis I can fit it. This resulted in the blue curves on the top two plots: the energy is best-fit (by eye, to a screenshot of the model; I didn't bother with curve extraction at the time), while the capacitance is pretty reasonably close, except for that bizarre hiccup at 10-15V. What the hell is up with that? Do they *check* these plots?
Aside: On a separate occasion, I've measured the STP19NM50N,
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and here it's plotted over the datasheet graph. See how it tanks like that? Yeah, the real thing doesn't tank like that. I suspect it's a plotting error (bad use of Bezier objects??), but crap like this /shouldn't make it into datasheets/.
So I suspect the energy curve isn't bad, and my model is probably a good fit to the real part.
Back to the 24A part's SPICE model. I set up a SPICE "test bench" to directly read off E(V) and C(V), and compared my models (using diodes of appropriate CJO, M and VJ) to the SPICE models. This is where I obtained the 24's erroneous curves, and corrected them.
In case you were curious, ST wasn't interested in my fix for their crummy model. ;-)
Finally, the bottom two plots show charging curves. These are generated by taking 1000 points (it's a big spreadsheet..) and solving the difference equation for the appropriate equivalent circuit.
The three sets of curves are for the '70 (hand-fitted), the '24 (from SPICE), and then the '70 model scaled to the '24's datasheet value (which is also the best-fit red curve in the middle graphs, so indeed this appears to be a geometry scaling only).
The "R (us)" curves are the resistor-charge-to-80% value. As you can see, this starts much the same as the CCS method, but has a terribly long tail, so tends to unfairly weight the capacitance at high voltages, which will give a low estimate.
The "CCS (us)" curves, of course, are simply by CCS alone. The OP circuit will generate this waveform, backwards of course.
In fuchsia, "ramp (us)" was only computed for the '70, and uses a linear current ramp to approximate an inductance. As you can see, it's practically diode recovery: it sits there, below 20V, for a long-ass time, then bolts like a spooked horse!
The final output numbers (from these curves) are given near the input parameters:
Res = resistive equivalent (100kohm resistor to +600V; equivalent is based on the time taken to 80%, or 480V) CCS = constant current time equivalent Cdss E_eff = energy equivalent ramp eff = inductive hard switching equivalent (my method).
As you can see, the equivalents are kind of all over the place; CCS makes the largest equivalent, while energy is the lowest. If you see one but not the other, you can probably guess a datasheet is trying to sell you something.
The model data is also present here: Cpar is fixed capacitance, CJO, m and VJ are diode parameters, and both models have two diodes in parallel (allowing two VJ breakpoints). Obviously, the one that's 0nF doesn't count, so a good fit was had with just the one.
The m values are quite large (ultrahyperabrupt?), whereas some SPICE engines limit it to 0.9 or something like that, for diodes. (Does anyone have any clue why? It's a completely arbitrary and superfluous limit!) So I also built a nonlinear dependent equivalent, which works fine on any SPICE.
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